25 #ifndef _E1000_DEFINES_H_
26 #define _E1000_DEFINES_H_
29 #define REQ_TX_DESCRIPTOR_MULTIPLE 8
30 #define REQ_RX_DESCRIPTOR_MULTIPLE 8
34 #define E1000_WUC_PME_EN 0x00000002
37 #define E1000_WUFC_LNKC 0x00000001
38 #define E1000_WUFC_MAG 0x00000002
39 #define E1000_WUFC_EX 0x00000004
40 #define E1000_WUFC_MC 0x00000008
41 #define E1000_WUFC_BC 0x00000010
44 #define E1000_CTRL_EXT_SDP2_DATA 0x00000040
45 #define E1000_CTRL_EXT_SDP3_DATA 0x00000080
46 #define E1000_CTRL_EXT_SDP2_DIR 0x00000400
47 #define E1000_CTRL_EXT_SDP3_DIR 0x00000800
50 #define E1000_CTRL_EXT_PFRSTD 0x00004000
51 #define E1000_CTRL_EXT_SDLPE 0X00040000
52 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
53 #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000
54 #define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX 0x00400000
55 #define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000
56 #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
57 #define E1000_CTRL_EXT_EIAME 0x01000000
58 #define E1000_CTRL_EXT_IRCA 0x00000001
61 #define E1000_CTRL_EXT_DRV_LOAD 0x10000000
66 #define E1000_CTRL_EXT_PBA_CLR 0x80000000
67 #define E1000_CTRL_EXT_PHYPDEN 0x00100000
68 #define E1000_I2CCMD_REG_ADDR_SHIFT 16
69 #define E1000_I2CCMD_PHY_ADDR_SHIFT 24
70 #define E1000_I2CCMD_OPCODE_READ 0x08000000
71 #define E1000_I2CCMD_OPCODE_WRITE 0x00000000
72 #define E1000_I2CCMD_READY 0x20000000
73 #define E1000_I2CCMD_ERROR 0x80000000
74 #define E1000_I2CCMD_SFP_DATA_ADDR(a) (0x0000 + (a))
75 #define E1000_I2CCMD_SFP_DIAG_ADDR(a) (0x0100 + (a))
76 #define E1000_MAX_SGMII_PHY_REG_ADDR 255
77 #define E1000_I2CCMD_PHY_TIMEOUT 200
78 #define E1000_IVAR_VALID 0x80
79 #define E1000_GPIE_NSICR 0x00000001
80 #define E1000_GPIE_MSIX_MODE 0x00000010
81 #define E1000_GPIE_EIAME 0x40000000
82 #define E1000_GPIE_PBA 0x80000000
85 #define E1000_RXD_STAT_DD 0x01
86 #define E1000_RXD_STAT_EOP 0x02
87 #define E1000_RXD_STAT_IXSM 0x04
88 #define E1000_RXD_STAT_VP 0x08
89 #define E1000_RXD_STAT_UDPCS 0x10
90 #define E1000_RXD_STAT_TCPCS 0x20
91 #define E1000_RXD_STAT_TS 0x10000
93 #define E1000_RXDEXT_STATERR_LB 0x00040000
94 #define E1000_RXDEXT_STATERR_CE 0x01000000
95 #define E1000_RXDEXT_STATERR_SE 0x02000000
96 #define E1000_RXDEXT_STATERR_SEQ 0x04000000
97 #define E1000_RXDEXT_STATERR_CXE 0x10000000
98 #define E1000_RXDEXT_STATERR_TCPE 0x20000000
99 #define E1000_RXDEXT_STATERR_IPE 0x40000000
100 #define E1000_RXDEXT_STATERR_RXE 0x80000000
103 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
104 E1000_RXDEXT_STATERR_CE | \
105 E1000_RXDEXT_STATERR_SE | \
106 E1000_RXDEXT_STATERR_SEQ | \
107 E1000_RXDEXT_STATERR_CXE | \
108 E1000_RXDEXT_STATERR_RXE)
110 #define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
111 #define E1000_MRQC_RSS_FIELD_IPV4 0x00020000
112 #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000
113 #define E1000_MRQC_RSS_FIELD_IPV6 0x00100000
114 #define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
118 #define E1000_MANC_SMBUS_EN 0x00000001
119 #define E1000_MANC_ASF_EN 0x00000002
120 #define E1000_MANC_EN_BMC2OS 0x10000000
122 #define E1000_MANC_RCV_TCO_EN 0x00020000
123 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000
125 #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000
128 #define E1000_RCTL_EN 0x00000002
129 #define E1000_RCTL_SBP 0x00000004
130 #define E1000_RCTL_UPE 0x00000008
131 #define E1000_RCTL_MPE 0x00000010
132 #define E1000_RCTL_LPE 0x00000020
133 #define E1000_RCTL_LBM_MAC 0x00000040
134 #define E1000_RCTL_LBM_TCVR 0x000000C0
135 #define E1000_RCTL_RDMTS_HALF 0x00000000
136 #define E1000_RCTL_MO_SHIFT 12
137 #define E1000_RCTL_BAM 0x00008000
138 #define E1000_RCTL_SZ_512 0x00020000
139 #define E1000_RCTL_SZ_256 0x00030000
140 #define E1000_RCTL_VFE 0x00040000
141 #define E1000_RCTL_CFIEN 0x00080000
142 #define E1000_RCTL_DPF 0x00400000
143 #define E1000_RCTL_PMCF 0x00800000
144 #define E1000_RCTL_SECRC 0x04000000
162 #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F
163 #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00
164 #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
165 #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
167 #define E1000_PSRCTL_BSIZE0_SHIFT 7
168 #define E1000_PSRCTL_BSIZE1_SHIFT 2
169 #define E1000_PSRCTL_BSIZE2_SHIFT 6
170 #define E1000_PSRCTL_BSIZE3_SHIFT 14
173 #define E1000_SWFW_EEP_SM 0x1
174 #define E1000_SWFW_PHY0_SM 0x2
175 #define E1000_SWFW_PHY1_SM 0x4
176 #define E1000_SWFW_PHY2_SM 0x20
177 #define E1000_SWFW_PHY3_SM 0x40
181 #define E1000_CTRL_FD 0x00000001
182 #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004
183 #define E1000_CTRL_LRST 0x00000008
184 #define E1000_CTRL_ASDE 0x00000020
185 #define E1000_CTRL_SLU 0x00000040
186 #define E1000_CTRL_ILOS 0x00000080
187 #define E1000_CTRL_SPD_SEL 0x00000300
188 #define E1000_CTRL_SPD_100 0x00000100
189 #define E1000_CTRL_SPD_1000 0x00000200
190 #define E1000_CTRL_FRCSPD 0x00000800
191 #define E1000_CTRL_FRCDPX 0x00001000
195 #define E1000_CTRL_SWDPIN0 0x00040000
196 #define E1000_CTRL_SWDPIN1 0x00080000
197 #define E1000_CTRL_SDP0_DIR 0x00400000
198 #define E1000_CTRL_SDP1_DIR 0x00800000
199 #define E1000_CTRL_RST 0x04000000
200 #define E1000_CTRL_RFCE 0x08000000
201 #define E1000_CTRL_TFCE 0x10000000
202 #define E1000_CTRL_VME 0x40000000
203 #define E1000_CTRL_PHY_RST 0x80000000
205 #define E1000_CTRL_I2C_ENA 0x02000000
211 #define E1000_CONNSW_ENRGSRC 0x4
212 #define E1000_CONNSW_PHYSD 0x400
213 #define E1000_CONNSW_PHY_PDN 0x800
214 #define E1000_CONNSW_SERDESD 0x200
215 #define E1000_CONNSW_AUTOSENSE_CONF 0x2
216 #define E1000_CONNSW_AUTOSENSE_EN 0x1
217 #define E1000_PCS_CFG_PCS_EN 8
218 #define E1000_PCS_LCTL_FLV_LINK_UP 1
219 #define E1000_PCS_LCTL_FSV_100 2
220 #define E1000_PCS_LCTL_FSV_1000 4
221 #define E1000_PCS_LCTL_FDV_FULL 8
222 #define E1000_PCS_LCTL_FSD 0x10
223 #define E1000_PCS_LCTL_FORCE_LINK 0x20
224 #define E1000_PCS_LCTL_FORCE_FCTRL 0x80
225 #define E1000_PCS_LCTL_AN_ENABLE 0x10000
226 #define E1000_PCS_LCTL_AN_RESTART 0x20000
227 #define E1000_PCS_LCTL_AN_TIMEOUT 0x40000
228 #define E1000_ENABLE_SERDES_LOOPBACK 0x0410
230 #define E1000_PCS_LSTS_LINK_OK 1
231 #define E1000_PCS_LSTS_SPEED_100 2
232 #define E1000_PCS_LSTS_SPEED_1000 4
233 #define E1000_PCS_LSTS_DUPLEX_FULL 8
234 #define E1000_PCS_LSTS_SYNK_OK 0x10
237 #define E1000_STATUS_FD 0x00000001
238 #define E1000_STATUS_LU 0x00000002
239 #define E1000_STATUS_FUNC_MASK 0x0000000C
240 #define E1000_STATUS_FUNC_SHIFT 2
241 #define E1000_STATUS_FUNC_1 0x00000004
242 #define E1000_STATUS_TXOFF 0x00000010
243 #define E1000_STATUS_SPEED_100 0x00000040
244 #define E1000_STATUS_SPEED_1000 0x00000080
247 #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000
250 #define E1000_STATUS_2P5_SKU 0x00001000
251 #define E1000_STATUS_2P5_SKU_OVER 0x00002000
255 #define SPEED_100 100
256 #define SPEED_1000 1000
257 #define SPEED_2500 2500
258 #define HALF_DUPLEX 1
259 #define FULL_DUPLEX 2
262 #define ADVERTISE_10_HALF 0x0001
263 #define ADVERTISE_10_FULL 0x0002
264 #define ADVERTISE_100_HALF 0x0004
265 #define ADVERTISE_100_FULL 0x0008
266 #define ADVERTISE_1000_HALF 0x0010
267 #define ADVERTISE_1000_FULL 0x0020
270 #define E1000_ALL_SPEED_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
271 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
273 #define E1000_ALL_NOT_GIG (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
274 ADVERTISE_100_HALF | ADVERTISE_100_FULL)
275 #define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL)
276 #define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL)
277 #define E1000_ALL_FULL_DUPLEX (ADVERTISE_10_FULL | ADVERTISE_100_FULL | \
279 #define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF)
281 #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX
284 #define E1000_LEDCTL_LED0_MODE_SHIFT 0
285 #define E1000_LEDCTL_LED0_BLINK 0x00000080
286 #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
287 #define E1000_LEDCTL_LED0_IVRT 0x00000040
289 #define E1000_LEDCTL_MODE_LED_ON 0xE
290 #define E1000_LEDCTL_MODE_LED_OFF 0xF
293 #define E1000_TXD_POPTS_IXSM 0x01
294 #define E1000_TXD_POPTS_TXSM 0x02
295 #define E1000_TXD_CMD_EOP 0x01000000
296 #define E1000_TXD_CMD_IFCS 0x02000000
297 #define E1000_TXD_CMD_RS 0x08000000
298 #define E1000_TXD_CMD_DEXT 0x20000000
299 #define E1000_TXD_STAT_DD 0x00000001
303 #define E1000_TCTL_EN 0x00000002
304 #define E1000_TCTL_PSP 0x00000008
305 #define E1000_TCTL_CT 0x00000ff0
306 #define E1000_TCTL_COLD 0x003ff000
307 #define E1000_TCTL_RTLC 0x01000000
310 #define E1000_DMACR_DMACWT_MASK 0x00003FFF
311 #define E1000_DMACR_DMACTHR_MASK 0x00FF0000
312 #define E1000_DMACR_DMACTHR_SHIFT 16
313 #define E1000_DMACR_DMAC_LX_MASK 0x30000000
314 #define E1000_DMACR_DMAC_LX_SHIFT 28
315 #define E1000_DMACR_DMAC_EN 0x80000000
317 #define E1000_DMACR_DC_BMC2OSW_EN 0x00008000
319 #define E1000_DMCTXTH_DMCTTHR_MASK 0x00000FFF
321 #define E1000_DMCTLX_TTLX_MASK 0x00000FFF
323 #define E1000_DMCRTRH_UTRESH_MASK 0x0007FFFF
324 #define E1000_DMCRTRH_LRPRCW 0x80000000
326 #define E1000_DMCCNT_CCOUNT_MASK 0x01FFFFFF
328 #define E1000_FCRTC_RTH_COAL_MASK 0x0003FFF0
329 #define E1000_FCRTC_RTH_COAL_SHIFT 4
330 #define E1000_PCIEMISC_LX_DECISION 0x00000080
333 #define E1000_RXPBS_CFG_TS_EN 0x80000000
335 #define I210_RXPBSIZE_DEFAULT 0x000000A2
336 #define I210_TXPBSIZE_DEFAULT 0x04000014
339 #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
342 #define E1000_RXCSUM_IPOFL 0x00000100
343 #define E1000_RXCSUM_TUOFL 0x00000200
344 #define E1000_RXCSUM_CRCOFL 0x00000800
345 #define E1000_RXCSUM_PCSD 0x00002000
348 #define E1000_RFCTL_IPV6_EX_DIS 0x00010000
349 #define E1000_RFCTL_LEF 0x00040000
352 #define E1000_COLLISION_THRESHOLD 15
353 #define E1000_CT_SHIFT 4
354 #define E1000_COLLISION_DISTANCE 63
355 #define E1000_COLD_SHIFT 12
358 #define ETHERNET_IEEE_VLAN_TYPE 0x8100
360 #define MAX_JUMBO_FRAME_SIZE 0x3F00
363 #define E1000_PBA_34K 0x0022
364 #define E1000_PBA_64K 0x0040
367 #define E1000_SWSM_SMBI 0x00000001
368 #define E1000_SWSM_SWESMBI 0x00000002
371 #define E1000_ICR_TXDW 0x00000001
372 #define E1000_ICR_LSC 0x00000004
373 #define E1000_ICR_RXSEQ 0x00000008
374 #define E1000_ICR_RXDMT0 0x00000010
375 #define E1000_ICR_RXT0 0x00000080
376 #define E1000_ICR_VMMB 0x00000100
377 #define E1000_ICR_TS 0x00080000
378 #define E1000_ICR_DRSTA 0x40000000
380 #define E1000_ICR_INT_ASSERTED 0x80000000
382 #define E1000_ICR_DOUTSYNC 0x10000000
385 #define E1000_EICR_RX_QUEUE0 0x00000001
386 #define E1000_EICR_RX_QUEUE1 0x00000002
387 #define E1000_EICR_RX_QUEUE2 0x00000004
388 #define E1000_EICR_RX_QUEUE3 0x00000008
389 #define E1000_EICR_TX_QUEUE0 0x00000100
390 #define E1000_EICR_TX_QUEUE1 0x00000200
391 #define E1000_EICR_TX_QUEUE2 0x00000400
392 #define E1000_EICR_TX_QUEUE3 0x00000800
393 #define E1000_EICR_OTHER 0x80000000
404 #define IMS_ENABLE_MASK ( \
413 #define E1000_IMS_TXDW E1000_ICR_TXDW
414 #define E1000_IMS_LSC E1000_ICR_LSC
415 #define E1000_IMS_VMMB E1000_ICR_VMMB
416 #define E1000_IMS_TS E1000_ICR_TS
417 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ
418 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0
419 #define E1000_IMS_RXT0 E1000_ICR_RXT0
420 #define E1000_IMS_DRSTA E1000_ICR_DRSTA
421 #define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC
424 #define E1000_EIMS_OTHER E1000_EICR_OTHER
427 #define E1000_ICS_LSC E1000_ICR_LSC
428 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0
429 #define E1000_ICS_DRSTA E1000_ICR_DRSTA
433 #define E1000_EITR_CNT_IGNR 0x80000000
440 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
441 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
442 #define FLOW_CONTROL_TYPE 0x8808
445 #define E1000_TXCW_ASM_DIR 0x00000100
446 #define E1000_TXCW_PAUSE 0x00000080
449 #define VLAN_TAG_SIZE 4
450 #define E1000_VLAN_FILTER_TBL_SIZE 128
459 #define E1000_RAH_AV 0x80000000
460 #define E1000_RAL_MAC_ADDR_LEN 4
461 #define E1000_RAH_MAC_ADDR_LEN 2
462 #define E1000_RAH_POOL_MASK 0x03FC0000
463 #define E1000_RAH_POOL_1 0x00040000
466 #define E1000_ERR_NVM 1
467 #define E1000_ERR_PHY 2
468 #define E1000_ERR_CONFIG 3
469 #define E1000_ERR_PARAM 4
470 #define E1000_ERR_MAC_INIT 5
471 #define E1000_ERR_RESET 9
472 #define E1000_ERR_MASTER_REQUESTS_PENDING 10
473 #define E1000_BLK_PHY_RESET 12
474 #define E1000_ERR_SWFW_SYNC 13
475 #define E1000_NOT_IMPLEMENTED 14
476 #define E1000_ERR_MBX 15
477 #define E1000_ERR_INVALID_ARGUMENT 16
478 #define E1000_ERR_NO_SPACE 17
479 #define E1000_ERR_NVM_PBA_SECTION 18
480 #define E1000_ERR_INVM_VALUE_NOT_FOUND 19
481 #define E1000_ERR_I2C 20
484 #define COPPER_LINK_UP_LIMIT 10
485 #define PHY_AUTO_NEG_LIMIT 45
486 #define PHY_FORCE_LIMIT 20
488 #define MASTER_DISABLE_TIMEOUT 800
490 #define PHY_CFG_TIMEOUT 100
493 #define AUTO_READ_DONE_TIMEOUT 10
496 #define E1000_FCRTL_XONE 0x80000000
498 #define E1000_TSYNCTXCTL_VALID 0x00000001
499 #define E1000_TSYNCTXCTL_ENABLED 0x00000010
501 #define E1000_TSYNCRXCTL_VALID 0x00000001
502 #define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E
503 #define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00
504 #define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02
505 #define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04
506 #define E1000_TSYNCRXCTL_TYPE_ALL 0x08
507 #define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A
508 #define E1000_TSYNCRXCTL_ENABLED 0x00000010
510 #define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK 0x000000FF
511 #define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE 0x00
512 #define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE 0x01
513 #define E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE 0x02
514 #define E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE 0x03
515 #define E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE 0x04
517 #define E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK 0x00000F00
518 #define E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE 0x0000
519 #define E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE 0x0100
520 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE 0x0200
521 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE 0x0300
522 #define E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE 0x0800
523 #define E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE 0x0900
524 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE 0x0A00
525 #define E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE 0x0B00
526 #define E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE 0x0C00
527 #define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE 0x0D00
529 #define E1000_TIMINCA_16NS_SHIFT 24
533 #define TSINTR_SYS_WRAP (1 << 0)
534 #define TSINTR_TXTS (1 << 1)
535 #define TSINTR_RXTS (1 << 2)
536 #define TSINTR_TT0 (1 << 3)
537 #define TSINTR_TT1 (1 << 4)
538 #define TSINTR_AUTT0 (1 << 5)
539 #define TSINTR_AUTT1 (1 << 6)
540 #define TSINTR_TADJ (1 << 7)
542 #define TSYNC_INTERRUPTS TSINTR_TXTS
543 #define E1000_TSICR_TXTS TSINTR_TXTS
546 #define TSAUXC_EN_TT0 (1 << 0)
547 #define TSAUXC_EN_TT1 (1 << 1)
548 #define TSAUXC_EN_CLK0 (1 << 2)
549 #define TSAUXC_SAMP_AUT0 (1 << 3)
550 #define TSAUXC_ST0 (1 << 4)
551 #define TSAUXC_EN_CLK1 (1 << 5)
552 #define TSAUXC_SAMP_AUT1 (1 << 6)
553 #define TSAUXC_ST1 (1 << 7)
554 #define TSAUXC_EN_TS0 (1 << 8)
555 #define TSAUXC_AUTT0 (1 << 9)
556 #define TSAUXC_EN_TS1 (1 << 10)
557 #define TSAUXC_AUTT1 (1 << 11)
558 #define TSAUXC_PLSG (1 << 17)
559 #define TSAUXC_DISABLE (1 << 31)
562 #define AUX0_SEL_SDP0 (0 << 0)
563 #define AUX0_SEL_SDP1 (1 << 0)
564 #define AUX0_SEL_SDP2 (2 << 0)
565 #define AUX0_SEL_SDP3 (3 << 0)
566 #define AUX0_TS_SDP_EN (1 << 2)
567 #define AUX1_SEL_SDP0 (0 << 3)
568 #define AUX1_SEL_SDP1 (1 << 3)
569 #define AUX1_SEL_SDP2 (2 << 3)
570 #define AUX1_SEL_SDP3 (3 << 3)
571 #define AUX1_TS_SDP_EN (1 << 5)
572 #define TS_SDP0_SEL_TT0 (0 << 6)
573 #define TS_SDP0_SEL_TT1 (1 << 6)
574 #define TS_SDP0_SEL_FC0 (2 << 6)
575 #define TS_SDP0_SEL_FC1 (3 << 6)
576 #define TS_SDP0_EN (1 << 8)
577 #define TS_SDP1_SEL_TT0 (0 << 9)
578 #define TS_SDP1_SEL_TT1 (1 << 9)
579 #define TS_SDP1_SEL_FC0 (2 << 9)
580 #define TS_SDP1_SEL_FC1 (3 << 9)
581 #define TS_SDP1_EN (1 << 11)
582 #define TS_SDP2_SEL_TT0 (0 << 12)
583 #define TS_SDP2_SEL_TT1 (1 << 12)
584 #define TS_SDP2_SEL_FC0 (2 << 12)
585 #define TS_SDP2_SEL_FC1 (3 << 12)
586 #define TS_SDP2_EN (1 << 14)
587 #define TS_SDP3_SEL_TT0 (0 << 15)
588 #define TS_SDP3_SEL_TT1 (1 << 15)
589 #define TS_SDP3_SEL_FC0 (2 << 15)
590 #define TS_SDP3_SEL_FC1 (3 << 15)
591 #define TS_SDP3_EN (1 << 17)
593 #define E1000_MDICNFG_EXT_MDIO 0x80000000
594 #define E1000_MDICNFG_COM_MDIO 0x40000000
595 #define E1000_MDICNFG_PHY_MASK 0x03E00000
596 #define E1000_MDICNFG_PHY_SHIFT 21
598 #define E1000_MEDIA_PORT_COPPER 1
599 #define E1000_MEDIA_PORT_OTHER 2
600 #define E1000_M88E1112_AUTO_COPPER_SGMII 0x2
601 #define E1000_M88E1112_AUTO_COPPER_BASEX 0x3
602 #define E1000_M88E1112_STATUS_LINK 0x0004
603 #define E1000_M88E1112_MAC_CTRL_1 0x10
604 #define E1000_M88E1112_MAC_CTRL_1_MODE_MASK 0x0380
605 #define E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT 7
606 #define E1000_M88E1112_PAGE_ADDR 0x16
607 #define E1000_M88E1112_STATUS 0x01
610 #define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000
611 #define E1000_GCR_CMPL_TMOUT_10ms 0x00001000
612 #define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000
613 #define E1000_GCR_CAP_VER2 0x00040000
616 #define E1000_MPHY_ADDR_CTL 0x0024
617 #define E1000_MPHY_ADDR_CTL_OFFSET_MASK 0xFFFF0000
618 #define E1000_MPHY_DATA 0x0E10
621 #define E1000_MPHY_PCS_CLK_REG_OFFSET 0x0004
623 #define E1000_MPHY_PCS_CLK_REG_DIGINELBEN 0x10
625 #define E1000_PCS_LCTL_FORCE_FCTRL 0x80
626 #define E1000_PCS_LSTS_AN_COMPLETE 0x10000
629 #define MII_CR_FULL_DUPLEX 0x0100
630 #define MII_CR_RESTART_AUTO_NEG 0x0200
631 #define MII_CR_POWER_DOWN 0x0800
632 #define MII_CR_AUTO_NEG_EN 0x1000
633 #define MII_CR_LOOPBACK 0x4000
634 #define MII_CR_RESET 0x8000
635 #define MII_CR_SPEED_1000 0x0040
636 #define MII_CR_SPEED_100 0x2000
637 #define MII_CR_SPEED_10 0x0000
640 #define MII_SR_LINK_STATUS 0x0004
641 #define MII_SR_AUTONEG_COMPLETE 0x0020
644 #define NWAY_AR_10T_HD_CAPS 0x0020
645 #define NWAY_AR_10T_FD_CAPS 0x0040
646 #define NWAY_AR_100TX_HD_CAPS 0x0080
647 #define NWAY_AR_100TX_FD_CAPS 0x0100
648 #define NWAY_AR_PAUSE 0x0400
649 #define NWAY_AR_ASM_DIR 0x0800
652 #define NWAY_LPAR_PAUSE 0x0400
653 #define NWAY_LPAR_ASM_DIR 0x0800
658 #define CR_1000T_HD_CAPS 0x0100
659 #define CR_1000T_FD_CAPS 0x0200
660 #define CR_1000T_MS_VALUE 0x0800
662 #define CR_1000T_MS_ENABLE 0x1000
666 #define SR_1000T_REMOTE_RX_STATUS 0x1000
667 #define SR_1000T_LOCAL_RX_STATUS 0x2000
672 #define PHY_CONTROL 0x00
673 #define PHY_STATUS 0x01
676 #define PHY_AUTONEG_ADV 0x04
677 #define PHY_LP_ABILITY 0x05
678 #define PHY_1000T_CTRL 0x09
679 #define PHY_1000T_STATUS 0x0A
682 #define E1000_EECD_SK 0x00000001
683 #define E1000_EECD_CS 0x00000002
684 #define E1000_EECD_DI 0x00000004
685 #define E1000_EECD_DO 0x00000008
686 #define E1000_EECD_REQ 0x00000040
687 #define E1000_EECD_GNT 0x00000080
688 #define E1000_EECD_PRES 0x00000100
690 #define E1000_EECD_ADDR_BITS 0x00000400
691 #define E1000_NVM_GRANT_ATTEMPTS 1000
692 #define E1000_EECD_AUTO_RD 0x00000200
693 #define E1000_EECD_SIZE_EX_MASK 0x00007800
694 #define E1000_EECD_SIZE_EX_SHIFT 11
695 #define E1000_EECD_FLUPD_I210 0x00800000
696 #define E1000_EECD_FLUDONE_I210 0x04000000
697 #define E1000_EECD_FLASH_DETECTED_I210 0x00080000
698 #define E1000_FLUDONE_ATTEMPTS 20000
699 #define E1000_EERD_EEWR_MAX_COUNT 512
700 #define E1000_I210_FIFO_SEL_RX 0x00
701 #define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i))
702 #define E1000_I210_FIFO_SEL_TX_LEGACY E1000_I210_FIFO_SEL_TX_QAV(0)
703 #define E1000_I210_FIFO_SEL_BMC2OS_TX 0x06
704 #define E1000_I210_FIFO_SEL_BMC2OS_RX 0x01
705 #define E1000_I210_FLASH_SECTOR_SIZE 0x1000
707 #define E1000_I210_FW_PTR_MASK 0x7FFF
709 #define E1000_I210_FW_VER_OFFSET 328
710 #define E1000_EECD_FLUPD_I210 0x00800000
711 #define E1000_EECD_FLUDONE_I210 0x04000000
712 #define E1000_FLUDONE_ATTEMPTS 20000
713 #define E1000_EERD_EEWR_MAX_COUNT 512
714 #define E1000_I210_FIFO_SEL_RX 0x00
715 #define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i))
716 #define E1000_I210_FIFO_SEL_TX_LEGACY E1000_I210_FIFO_SEL_TX_QAV(0)
717 #define E1000_I210_FIFO_SEL_BMC2OS_TX 0x06
718 #define E1000_I210_FIFO_SEL_BMC2OS_RX 0x01
722 #define E1000_NVM_RW_REG_DATA 16
723 #define E1000_NVM_RW_REG_DONE 2
724 #define E1000_NVM_RW_REG_START 1
725 #define E1000_NVM_RW_ADDR_SHIFT 2
726 #define E1000_NVM_POLL_READ 0
729 #define NVM_COMPAT 0x0003
730 #define NVM_ID_LED_SETTINGS 0x0004
731 #define NVM_VERSION 0x0005
732 #define NVM_INIT_CONTROL2_REG 0x000F
733 #define NVM_INIT_CONTROL3_PORT_B 0x0014
734 #define NVM_INIT_CONTROL3_PORT_A 0x0024
735 #define NVM_ALT_MAC_ADDR_PTR 0x0037
736 #define NVM_CHECKSUM_REG 0x003F
737 #define NVM_COMPATIBILITY_REG_3 0x0003
738 #define NVM_COMPATIBILITY_BIT_MASK 0x8000
739 #define NVM_MAC_ADDR 0x0000
740 #define NVM_SUB_DEV_ID 0x000B
741 #define NVM_SUB_VEN_ID 0x000C
742 #define NVM_DEV_ID 0x000D
743 #define NVM_VEN_ID 0x000E
744 #define NVM_INIT_CTRL_2 0x000F
745 #define NVM_INIT_CTRL_4 0x0013
746 #define NVM_LED_1_CFG 0x001C
747 #define NVM_LED_0_2_CFG 0x001F
748 #define NVM_ETRACK_WORD 0x0042
749 #define NVM_ETRACK_HIWORD 0x0043
750 #define NVM_COMB_VER_OFF 0x0083
751 #define NVM_COMB_VER_PTR 0x003d
754 #define NVM_MAJOR_MASK 0xF000
755 #define NVM_MINOR_MASK 0x0FF0
756 #define NVM_IMAGE_ID_MASK 0x000F
757 #define NVM_COMB_VER_MASK 0x00FF
758 #define NVM_MAJOR_SHIFT 12
759 #define NVM_MINOR_SHIFT 4
760 #define NVM_COMB_VER_SHFT 8
761 #define NVM_VER_INVALID 0xFFFF
762 #define NVM_ETRACK_SHIFT 16
763 #define NVM_ETRACK_VALID 0x8000
764 #define NVM_NEW_DEC_MASK 0x0F00
765 #define NVM_HEX_CONV 16
766 #define NVM_HEX_TENS 10
768 #define NVM_ETS_CFG 0x003E
769 #define NVM_ETS_LTHRES_DELTA_MASK 0x07C0
770 #define NVM_ETS_LTHRES_DELTA_SHIFT 6
771 #define NVM_ETS_TYPE_MASK 0x0038
772 #define NVM_ETS_TYPE_SHIFT 3
773 #define NVM_ETS_TYPE_EMC 0x000
774 #define NVM_ETS_NUM_SENSORS_MASK 0x0007
775 #define NVM_ETS_DATA_LOC_MASK 0x3C00
776 #define NVM_ETS_DATA_LOC_SHIFT 10
777 #define NVM_ETS_DATA_INDEX_MASK 0x0300
778 #define NVM_ETS_DATA_INDEX_SHIFT 8
779 #define NVM_ETS_DATA_HTHRESH_MASK 0x00FF
781 #define E1000_NVM_CFG_DONE_PORT_0 0x040000
782 #define E1000_NVM_CFG_DONE_PORT_1 0x080000
783 #define E1000_NVM_CFG_DONE_PORT_2 0x100000
784 #define E1000_NVM_CFG_DONE_PORT_3 0x200000
786 #define NVM_82580_LAN_FUNC_OFFSET(a) (a ? (0x40 + (0x40 * a)) : 0)
789 #define NVM_WORD24_COM_MDIO 0x0008
790 #define NVM_WORD24_EXT_MDIO 0x0004
793 #define NVM_WORD0F_PAUSE_MASK 0x3000
794 #define NVM_WORD0F_ASM_DIR 0x2000
799 #define E1000_PBANUM_LENGTH 11
802 #define NVM_SUM 0xBABA
804 #define NVM_PBA_OFFSET_0 8
805 #define NVM_PBA_OFFSET_1 9
806 #define NVM_RESERVED_WORD 0xFFFF
807 #define NVM_PBA_PTR_GUARD 0xFAFA
808 #define NVM_WORD_SIZE_BASE_SHIFT 6
813 #define NVM_MAX_RETRY_SPI 5000
814 #define NVM_WRITE_OPCODE_SPI 0x02
815 #define NVM_READ_OPCODE_SPI 0x03
816 #define NVM_A8_OPCODE_SPI 0x08
817 #define NVM_WREN_OPCODE_SPI 0x06
818 #define NVM_RDSR_OPCODE_SPI 0x05
821 #define NVM_STATUS_RDY_SPI 0x01
824 #define ID_LED_RESERVED_0000 0x0000
825 #define ID_LED_RESERVED_FFFF 0xFFFF
826 #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
827 (ID_LED_OFF1_OFF2 << 8) | \
828 (ID_LED_DEF1_DEF2 << 4) | \
830 #define ID_LED_DEF1_DEF2 0x1
831 #define ID_LED_DEF1_ON2 0x2
832 #define ID_LED_DEF1_OFF2 0x3
833 #define ID_LED_ON1_DEF2 0x4
834 #define ID_LED_ON1_ON2 0x5
835 #define ID_LED_ON1_OFF2 0x6
836 #define ID_LED_OFF1_DEF2 0x7
837 #define ID_LED_OFF1_ON2 0x8
838 #define ID_LED_OFF1_OFF2 0x9
840 #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
841 #define IGP_ACTIVITY_LED_ENABLE 0x0300
842 #define IGP_LED3_MODE 0x07000000
845 #define PCIE_DEVICE_CONTROL2 0x28
846 #define PCIE_DEVICE_CONTROL2_16ms 0x0005
848 #define PHY_REVISION_MASK 0xFFFFFFF0
849 #define MAX_PHY_REG_ADDRESS 0x1F
850 #define MAX_PHY_MULTI_PAGE_REG 0xF
856 #define M88E1111_I_PHY_ID 0x01410CC0
857 #define M88E1112_E_PHY_ID 0x01410C90
858 #define I347AT4_E_PHY_ID 0x01410DC0
859 #define IGP03E1000_E_PHY_ID 0x02A80390
860 #define I82580_I_PHY_ID 0x015403A0
861 #define I350_I_PHY_ID 0x015403B0
862 #define M88_VENDOR 0x0141
863 #define I210_I_PHY_ID 0x01410C00
864 #define M88E1543_E_PHY_ID 0x01410EA0
867 #define M88E1000_PHY_SPEC_CTRL 0x10
868 #define M88E1000_PHY_SPEC_STATUS 0x11
869 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14
871 #define M88E1000_PHY_PAGE_SELECT 0x1D
872 #define M88E1000_PHY_GEN_CONTROL 0x1E
875 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002
877 #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000
879 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020
881 #define M88E1000_PSCR_AUTO_X_1000T 0x0040
883 #define M88E1000_PSCR_AUTO_X_MODE 0x0060
888 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800
891 #define M88E1000_PSSR_REV_POLARITY 0x0002
892 #define M88E1000_PSSR_DOWNSHIFT 0x0020
893 #define M88E1000_PSSR_MDIX 0x0040
900 #define M88E1000_PSSR_CABLE_LENGTH 0x0380
901 #define M88E1000_PSSR_SPEED 0xC000
902 #define M88E1000_PSSR_1000MBS 0x8000
904 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
915 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
916 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
920 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
921 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
922 #define M88E1000_EPSCR_TX_CLK_25 0x0070
926 #define I347AT4_PCDL 0x10
927 #define I347AT4_PCDC 0x15
928 #define I347AT4_PAGE_SELECT 0x16
935 #define I347AT4_PSCR_DOWNSHIFT_ENABLE 0x0800
936 #define I347AT4_PSCR_DOWNSHIFT_MASK 0x7000
937 #define I347AT4_PSCR_DOWNSHIFT_1X 0x0000
938 #define I347AT4_PSCR_DOWNSHIFT_2X 0x1000
939 #define I347AT4_PSCR_DOWNSHIFT_3X 0x2000
940 #define I347AT4_PSCR_DOWNSHIFT_4X 0x3000
941 #define I347AT4_PSCR_DOWNSHIFT_5X 0x4000
942 #define I347AT4_PSCR_DOWNSHIFT_6X 0x5000
943 #define I347AT4_PSCR_DOWNSHIFT_7X 0x6000
944 #define I347AT4_PSCR_DOWNSHIFT_8X 0x7000
947 #define I347AT4_PCDC_CABLE_LENGTH_UNIT 0x0400
950 #define M88E1112_VCT_DSP_DISTANCE 0x001A
953 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
954 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
957 #define E1000_MDIC_DATA_MASK 0x0000FFFF
958 #define E1000_MDIC_REG_MASK 0x001F0000
959 #define E1000_MDIC_REG_SHIFT 16
960 #define E1000_MDIC_PHY_MASK 0x03E00000
961 #define E1000_MDIC_PHY_SHIFT 21
962 #define E1000_MDIC_OP_WRITE 0x04000000
963 #define E1000_MDIC_OP_READ 0x08000000
964 #define E1000_MDIC_READY 0x10000000
965 #define E1000_MDIC_INT_EN 0x20000000
966 #define E1000_MDIC_ERROR 0x40000000
967 #define E1000_MDIC_DEST 0x80000000
970 #define E1000_THSTAT_PWR_DOWN 0x00000001
971 #define E1000_THSTAT_LINK_THROTTLE 0x00000002
974 #define E1000_IPCNFG_EEE_1G_AN 0x00000008
975 #define E1000_IPCNFG_EEE_100M_AN 0x00000004
976 #define E1000_EEER_TX_LPI_EN 0x00010000
977 #define E1000_EEER_RX_LPI_EN 0x00020000
978 #define E1000_EEER_FRC_AN 0x10000000
979 #define E1000_EEER_LPI_FC 0x00040000
980 #define E1000_EEE_SU_LPI_CLK_STP 0X00800000
981 #define E1000_EEER_EEE_NEG 0x20000000
982 #define E1000_EEE_LP_ADV_ADDR_I350 0x040F
983 #define E1000_EEE_LP_ADV_DEV_I210 7
984 #define E1000_EEE_LP_ADV_ADDR_I210 61
985 #define E1000_MMDAC_FUNC_DATA 0x4000
986 #define E1000_M88E1543_PAGE_ADDR 0x16
987 #define E1000_M88E1543_EEE_CTRL_1 0x0
988 #define E1000_M88E1543_EEE_CTRL_1_MS 0x0001
989 #define E1000_EEE_ADV_DEV_I354 7
990 #define E1000_EEE_ADV_ADDR_I354 60
991 #define E1000_EEE_ADV_100_SUPPORTED (1 << 1)
992 #define E1000_EEE_ADV_1000_SUPPORTED (1 << 2)
993 #define E1000_PCS_STATUS_DEV_I354 3
994 #define E1000_PCS_STATUS_ADDR_I354 1
995 #define E1000_PCS_STATUS_TX_LPI_IND 0x0200
996 #define E1000_PCS_STATUS_RX_LPI_RCVD 0x0400
997 #define E1000_PCS_STATUS_TX_LPI_RCVD 0x0800
1000 #define E1000_GEN_CTL_READY 0x80000000
1001 #define E1000_GEN_CTL_ADDRESS_SHIFT 8
1002 #define E1000_GEN_POLL_TIMEOUT 640
1004 #define E1000_VFTA_ENTRY_SHIFT 5
1005 #define E1000_VFTA_ENTRY_MASK 0x7F
1006 #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
1009 #define E1000_PCIEMISC_LX_DECISION 0x00000080
1012 #define E1000_RTTBCNRC_RS_ENA 0x80000000
1013 #define E1000_RTTBCNRC_RF_DEC_MASK 0x00003FFF
1014 #define E1000_RTTBCNRC_RF_INT_SHIFT 14
1015 #define E1000_RTTBCNRC_RF_INT_MASK \
1016 (E1000_RTTBCNRC_RF_DEC_MASK << E1000_RTTBCNRC_RF_INT_SHIFT)