43 typedef unsigned char byte;
44 typedef unsigned short word;
45 typedef unsigned long int dword;
50 #define SMC_IO_EXTENT 16
73 #define BANK_SELECT 14
77 #define TCR_REG 0x0000
78 #define TCR_ENABLE 0x0001
79 #define TCR_LOOP 0x0002
80 #define TCR_FORCOL 0x0004
81 #define TCR_PAD_EN 0x0080
82 #define TCR_NOCRC 0x0100
83 #define TCR_MON_CSN 0x0400
84 #define TCR_FDUPLX 0x0800
85 #define TCR_STP_SQET 0x1000
86 #define TCR_EPH_LOOP 0x2000
87 #define TCR_SWFDUP 0x8000
92 #define TCR_DEFAULT TCR_ENABLE
97 #define EPH_STATUS_REG 0x0002
98 #define ES_TX_SUC 0x0001
99 #define ES_SNGL_COL 0x0002
100 #define ES_MUL_COL 0x0004
101 #define ES_LTX_MULT 0x0008
102 #define ES_16COL 0x0010
103 #define ES_SQET 0x0020
104 #define ES_LTXBRD 0x0040
105 #define ES_TXDEFR 0x0080
106 #define ES_LATCOL 0x0200
107 #define ES_LOSTCARR 0x0400
108 #define ES_EXC_DEF 0x0800
109 #define ES_CTR_ROL 0x1000
110 #define ES_LINK_OK 0x4000
111 #define ES_TXUNRN 0x8000
116 #define RCR_REG 0x0004
117 #define RCR_RX_ABORT 0x0001
118 #define RCR_PRMS 0x0002
119 #define RCR_ALMUL 0x0004
120 #define RCR_RXEN 0x0100
121 #define RCR_STRIP_CRC 0x0200
122 #define RCR_ABORT_ENB 0x0200
123 #define RCR_FILT_CAR 0x0400
124 #define RCR_SOFTRST 0x8000
127 #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
128 #define RCR_CLEAR 0x0
132 #define COUNTER_REG 0x0006
136 #define MIR_REG 0x0008
140 #define RPC_REG 0x000A
141 #define RPC_SPEED 0x2000
142 #define RPC_DPLX 0x1000
143 #define RPC_ANEG 0x0800
144 #define RPC_LSXA_SHFT 5
145 #define RPC_LSXB_SHFT 2
146 #define RPC_LED_100_10 (0x00)
147 #define RPC_LED_RES (0x01)
148 #define RPC_LED_10 (0x02)
149 #define RPC_LED_FD (0x03)
150 #define RPC_LED_TX_RX (0x04)
151 #define RPC_LED_100 (0x05)
152 #define RPC_LED_TX (0x06)
153 #define RPC_LED_RX (0x07)
154 #define RPC_DEFAULT (RPC_ANEG | (RPC_LED_100 << RPC_LSXA_SHFT) | (RPC_LED_FD << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
160 #define BSR_REG 0x000E
165 #define CONFIG_REG 0x0000
166 #define CONFIG_EXT_PHY 0x0200
167 #define CONFIG_GPCNTRL 0x0400
168 #define CONFIG_NO_WAIT 0x1000
169 #define CONFIG_EPH_POWER_EN 0x8000
172 #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
177 #define BASE_REG 0x0002
182 #define ADDR0_REG 0x0004
183 #define ADDR1_REG 0x0006
184 #define ADDR2_REG 0x0008
189 #define GP_REG 0x000A
194 #define CTL_REG 0x000C
195 #define CTL_RCV_BAD 0x4000
196 #define CTL_AUTO_RELEASE 0x0800
197 #define CTL_LE_ENABLE 0x0080
198 #define CTL_CR_ENABLE 0x0040
199 #define CTL_TE_ENABLE 0x0020
200 #define CTL_EEPROM_SELECT 0x0004
201 #define CTL_RELOAD 0x0002
202 #define CTL_STORE 0x0001
207 #define MMU_CMD_REG 0x0000
209 #define MC_NOP (0<<5)
210 #define MC_ALLOC (1<<5)
211 #define MC_RESET (2<<5)
212 #define MC_REMOVE (3<<5)
213 #define MC_RELEASE (4<<5)
214 #define MC_FREEPKT (5<<5)
215 #define MC_ENQUEUE (6<<5)
216 #define MC_RSTTXFIFO (7<<5)
221 #define PN_REG 0x0002
226 #define AR_REG 0x0003
227 #define AR_FAILED 0x80
232 #define RXFIFO_REG 0x0004
233 #define RXFIFO_REMPTY 0x8000
238 #define TXFIFO_REG RXFIFO_REG
239 #define TXFIFO_TEMPTY 0x80
244 #define PTR_REG 0x0006
245 #define PTR_RCV 0x8000
246 #define PTR_AUTOINC 0x4000
247 #define PTR_READ 0x2000
252 #define DATA_REG 0x0008
257 #define INT_REG 0x000C
262 #define IM_REG 0x000D
263 #define IM_MDINT 0x80
264 #define IM_ERCV_INT 0x40
265 #define IM_EPH_INT 0x20
266 #define IM_RX_OVRN_INT 0x10
267 #define IM_ALLOC_INT 0x08
268 #define IM_TX_EMPTY_INT 0x04
269 #define IM_TX_INT 0x02
270 #define IM_RCV_INT 0x01
275 #define MCAST_REG1 0x0000
276 #define MCAST_REG2 0x0002
277 #define MCAST_REG3 0x0004
278 #define MCAST_REG4 0x0006
283 #define MII_REG 0x0008
284 #define MII_MSK_CRS100 0x4000
285 #define MII_MDOE 0x0008
286 #define MII_MCLK 0x0004
287 #define MII_MDI 0x0002
288 #define MII_MDO 0x0001
293 #define REV_REG 0x000A
299 #define ERCV_REG 0x000C
300 #define ERCV_RCV_DISCRD 0x0080
301 #define ERCV_THRESHOLD 0x001F
305 #define EXT_REG 0x0000
313 #define CHIP_91100FD 8
314 #define CHIP_91111FD 9
316 static const char * chip_ids[ 15 ] = {
331 #define TS_SUCCESS 0x0001
332 #define TS_LOSTCAR 0x0400
333 #define TS_LATCOL 0x0200
334 #define TS_16COL 0x0010
339 #define RS_ALGNERR 0x8000
340 #define RS_BRODCAST 0x4000
341 #define RS_BADCRC 0x2000
342 #define RS_ODDFRAME 0x1000
343 #define RS_TOOLONG 0x0800
344 #define RS_TOOSHORT 0x0400
345 #define RS_MULTICAST 0x0001
346 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
359 #define PHY_CNTL_REG 0x00
360 #define PHY_CNTL_RST 0x8000
361 #define PHY_CNTL_LPBK 0x4000
362 #define PHY_CNTL_SPEED 0x2000
363 #define PHY_CNTL_ANEG_EN 0x1000
364 #define PHY_CNTL_PDN 0x0800
365 #define PHY_CNTL_MII_DIS 0x0400
366 #define PHY_CNTL_ANEG_RST 0x0200
367 #define PHY_CNTL_DPLX 0x0100
368 #define PHY_CNTL_COLTST 0x0080
371 #define PHY_STAT_REG 0x01
372 #define PHY_STAT_CAP_T4 0x8000
373 #define PHY_STAT_CAP_TXF 0x4000
374 #define PHY_STAT_CAP_TXH 0x2000
375 #define PHY_STAT_CAP_TF 0x1000
376 #define PHY_STAT_CAP_TH 0x0800
377 #define PHY_STAT_CAP_SUPR 0x0040
378 #define PHY_STAT_ANEG_ACK 0x0020
379 #define PHY_STAT_REM_FLT 0x0010
380 #define PHY_STAT_CAP_ANEG 0x0008
381 #define PHY_STAT_LINK 0x0004
382 #define PHY_STAT_JAB 0x0002
383 #define PHY_STAT_EXREG 0x0001
386 #define PHY_ID1_REG 0x02
387 #define PHY_ID2_REG 0x03
390 #define PHY_AD_REG 0x04
391 #define PHY_AD_NP 0x8000
392 #define PHY_AD_ACK 0x4000
393 #define PHY_AD_RF 0x2000
394 #define PHY_AD_T4 0x0200
395 #define PHY_AD_TX_FDX 0x0100
396 #define PHY_AD_TX_HDX 0x0080
397 #define PHY_AD_10_FDX 0x0040
398 #define PHY_AD_10_HDX 0x0020
399 #define PHY_AD_CSMA 0x0001
402 #define PHY_RMT_REG 0x05
406 #define PHY_CFG1_REG 0x10
407 #define PHY_CFG1_LNKDIS 0x8000
408 #define PHY_CFG1_XMTDIS 0x4000
409 #define PHY_CFG1_XMTPDN 0x2000
410 #define PHY_CFG1_BYPSCR 0x0400
411 #define PHY_CFG1_UNSCDS 0x0200
412 #define PHY_CFG1_EQLZR 0x0100
413 #define PHY_CFG1_CABLE 0x0080
414 #define PHY_CFG1_RLVL0 0x0040
415 #define PHY_CFG1_TLVL_SHIFT 2
416 #define PHY_CFG1_TLVL_MASK 0x003C
417 #define PHY_CFG1_TRF_MASK 0x0003
421 #define PHY_CFG2_REG 0x11
422 #define PHY_CFG2_APOLDIS 0x0020
423 #define PHY_CFG2_JABDIS 0x0010
424 #define PHY_CFG2_MREG 0x0008
425 #define PHY_CFG2_INTMDIO 0x0004
428 #define PHY_INT_REG 0x12
429 #define PHY_INT_INT 0x8000
430 #define PHY_INT_LNKFAIL 0x4000
431 #define PHY_INT_LOSSSYNC 0x2000
432 #define PHY_INT_CWRD 0x1000
433 #define PHY_INT_SSD 0x0800
434 #define PHY_INT_ESD 0x0400
435 #define PHY_INT_RPOL 0x0200
436 #define PHY_INT_JAB 0x0100
437 #define PHY_INT_SPDDET 0x0080
438 #define PHY_INT_DPLXDET 0x0040
441 #define PHY_MASK_REG 0x13
453 #define SMC_SELECT_BANK(x) { outw( x, ioaddr + BANK_SELECT ); }
456 #define SMC_ENABLE_INT(x) {\
459 mask = inb( ioaddr + IM_REG );\
461 outb( mask, ioaddr + IM_REG ); \
466 #define SMC_DISABLE_INT(x) {\
469 mask = inb( ioaddr + IM_REG );\
471 outb( mask, ioaddr + IM_REG ); \
483 #define SMC_INTERRUPT_MASK (IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | \
496 #define CTL_SMC (CTL_BUS+1389)