25 #ifndef _E1000_82575_H_
26 #define _E1000_82575_H_
28 void igb_shutdown_serdes_link_82575(
struct e1000_hw *hw);
29 void igb_power_up_serdes_link_82575(
struct e1000_hw *hw);
30 void igb_power_down_phy_copper_82575(
struct e1000_hw *hw);
31 void igb_rx_fifo_flush_82575(
struct e1000_hw *hw);
32 s32 igb_read_i2c_byte(
struct e1000_hw *hw, u8 byte_offset, u8 dev_addr,
34 s32 igb_write_i2c_byte(
struct e1000_hw *hw, u8 byte_offset, u8 dev_addr,
37 #define ID_LED_DEFAULT_82575_SERDES ((ID_LED_DEF1_DEF2 << 12) | \
38 (ID_LED_DEF1_DEF2 << 8) | \
39 (ID_LED_DEF1_DEF2 << 4) | \
42 #define E1000_RAR_ENTRIES_82575 16
43 #define E1000_RAR_ENTRIES_82576 24
44 #define E1000_RAR_ENTRIES_82580 24
45 #define E1000_RAR_ENTRIES_I350 32
47 #define E1000_SW_SYNCH_MB 0x00000100
48 #define E1000_STAT_DEV_RST_SET 0x00100000
49 #define E1000_CTRL_DEV_RST 0x20000000
52 #define E1000_SRRCTL_BSIZEPKT_SHIFT 10
53 #define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2
54 #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
55 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
56 #define E1000_SRRCTL_DROP_EN 0x80000000
57 #define E1000_SRRCTL_TIMESTAMP 0x40000000
60 #define E1000_MRQC_ENABLE_RSS_4Q 0x00000002
61 #define E1000_MRQC_ENABLE_VMDQ 0x00000003
62 #define E1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
63 #define E1000_MRQC_ENABLE_VMDQ_RSS_2Q 0x00000005
64 #define E1000_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
65 #define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000
67 #define E1000_EICR_TX_QUEUE ( \
68 E1000_EICR_TX_QUEUE0 | \
69 E1000_EICR_TX_QUEUE1 | \
70 E1000_EICR_TX_QUEUE2 | \
73 #define E1000_EICR_RX_QUEUE ( \
74 E1000_EICR_RX_QUEUE0 | \
75 E1000_EICR_RX_QUEUE1 | \
76 E1000_EICR_RX_QUEUE2 | \
80 #define E1000_IMIREXT_SIZE_BP 0x00001000
81 #define E1000_IMIREXT_CTRL_BP 0x00080000
84 union e1000_adv_rx_desc {
111 #define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0
112 #define E1000_RXDADV_HDRBUFLEN_SHIFT 5
113 #define E1000_RXDADV_STAT_TS 0x10000
114 #define E1000_RXDADV_STAT_TSIP 0x08000
117 union e1000_adv_tx_desc {
121 __le32 olinfo_status;
131 #define E1000_ADVTXD_MAC_TSTAMP 0x00080000
132 #define E1000_ADVTXD_DTYP_CTXT 0x00200000
133 #define E1000_ADVTXD_DTYP_DATA 0x00300000
134 #define E1000_ADVTXD_DCMD_EOP 0x01000000
135 #define E1000_ADVTXD_DCMD_IFCS 0x02000000
136 #define E1000_ADVTXD_DCMD_RS 0x08000000
137 #define E1000_ADVTXD_DCMD_DEXT 0x20000000
138 #define E1000_ADVTXD_DCMD_VLE 0x40000000
139 #define E1000_ADVTXD_DCMD_TSE 0x80000000
140 #define E1000_ADVTXD_PAYLEN_SHIFT 14
143 struct e1000_adv_tx_context_desc {
144 __le32 vlan_macip_lens;
146 __le32 type_tucmd_mlhl;
147 __le32 mss_l4len_idx;
150 #define E1000_ADVTXD_MACLEN_SHIFT 9
151 #define E1000_ADVTXD_TUCMD_IPV4 0x00000400
152 #define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800
153 #define E1000_ADVTXD_TUCMD_L4T_SCTP 0x00001000
155 #define E1000_ADVTXD_L4LEN_SHIFT 8
156 #define E1000_ADVTXD_MSS_SHIFT 16
161 #define E1000_TXDCTL_QUEUE_ENABLE 0x02000000
165 #define E1000_RXDCTL_QUEUE_ENABLE 0x02000000
168 #define E1000_DCA_CTRL_DCA_MODE_DISABLE 0x01
169 #define E1000_DCA_CTRL_DCA_MODE_CB2 0x02
171 #define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F
172 #define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5)
173 #define E1000_DCA_RXCTRL_HEAD_DCA_EN (1 << 6)
174 #define E1000_DCA_RXCTRL_DATA_DCA_EN (1 << 7)
175 #define E1000_DCA_RXCTRL_DESC_RRO_EN (1 << 9)
177 #define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F
178 #define E1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5)
179 #define E1000_DCA_TXCTRL_DESC_RRO_EN (1 << 9)
180 #define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11)
181 #define E1000_DCA_TXCTRL_DATA_RRO_EN (1 << 13)
184 #define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000
185 #define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000
186 #define E1000_DCA_TXCTRL_CPUID_SHIFT 24
187 #define E1000_DCA_RXCTRL_CPUID_SHIFT 24
190 #define E1000_ETQF_FILTER_ENABLE (1 << 26)
191 #define E1000_ETQF_1588 (1 << 30)
194 #define E1000_FTQF_VF_BP 0x00008000
195 #define E1000_FTQF_1588_TIME_STAMP 0x08000000
196 #define E1000_FTQF_MASK 0xF0000000
197 #define E1000_FTQF_MASK_PROTO_BP 0x10000000
198 #define E1000_FTQF_MASK_SOURCE_PORT_BP 0x80000000
200 #define E1000_NVM_APME_82575 0x0400
201 #define MAX_NUM_VFS 8
203 #define E1000_DTXSWC_MAC_SPOOF_MASK 0x000000FF
204 #define E1000_DTXSWC_VLAN_SPOOF_MASK 0x0000FF00
205 #define E1000_DTXSWC_LLE_MASK 0x00FF0000
206 #define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8
207 #define E1000_DTXSWC_VMDQ_LOOPBACK_EN (1 << 31)
210 #define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7
211 #define E1000_VT_CTL_DEFAULT_POOL_MASK (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT)
214 #define E1000_VT_CTL_IGNORE_MAC (1 << 28)
215 #define E1000_VT_CTL_DISABLE_DEF_POOL (1 << 29)
216 #define E1000_VT_CTL_VM_REPL_EN (1 << 30)
219 #define E1000_VMOLR_RLPML_MASK 0x00003FFF
220 #define E1000_VMOLR_LPE 0x00010000
221 #define E1000_VMOLR_RSSE 0x00020000
222 #define E1000_VMOLR_AUPE 0x01000000
223 #define E1000_VMOLR_ROMPE 0x02000000
224 #define E1000_VMOLR_ROPE 0x04000000
225 #define E1000_VMOLR_BAM 0x08000000
226 #define E1000_VMOLR_MPME 0x10000000
227 #define E1000_VMOLR_STRVLAN 0x40000000
228 #define E1000_VMOLR_STRCRC 0x80000000
230 #define E1000_DVMOLR_HIDEVLAN 0x20000000
231 #define E1000_DVMOLR_STRVLAN 0x40000000
232 #define E1000_DVMOLR_STRCRC 0x80000000
234 #define E1000_VLVF_ARRAY_SIZE 32
235 #define E1000_VLVF_VLANID_MASK 0x00000FFF
236 #define E1000_VLVF_POOLSEL_SHIFT 12
237 #define E1000_VLVF_POOLSEL_MASK (0xFF << E1000_VLVF_POOLSEL_SHIFT)
238 #define E1000_VLVF_LVLAN 0x00100000
239 #define E1000_VLVF_VLANID_ENABLE 0x80000000
241 #define E1000_VMVIR_VLANA_DEFAULT 0x40000000
242 #define E1000_VMVIR_VLANA_NEVER 0x80000000
244 #define E1000_IOVCTL 0x05BBC
245 #define E1000_IOVCTL_REUSE_VFQ 0x00000001
247 #define E1000_RPLOLR_STRVLAN 0x40000000
248 #define E1000_RPLOLR_STRCRC 0x80000000
250 #define E1000_DTXCTL_8023LL 0x0004
251 #define E1000_DTXCTL_VLAN_ADDED 0x0008
252 #define E1000_DTXCTL_OOS_ENABLE 0x0010
253 #define E1000_DTXCTL_MDP_EN 0x0020
254 #define E1000_DTXCTL_SPOOF_INT 0x0040
256 #define E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT (1 << 14)
258 #define ALL_QUEUES 0xFFFF
261 #define E1000_RXPBS_SIZE_MASK_82576 0x0000007F
262 void igb_vmdq_set_anti_spoofing_pf(
struct e1000_hw *,
bool,
int);
263 void igb_vmdq_set_loopback_pf(
struct e1000_hw *,
bool);
264 void igb_vmdq_set_replication_pf(
struct e1000_hw *,
bool);
265 u16 igb_rxpbs_adjust_82580(u32 data);
266 s32 igb_read_emi_reg(
struct e1000_hw *, u16 addr, u16 *data);
267 s32 igb_set_eee_i350(
struct e1000_hw *,
bool adv1G,
bool adv100M);
268 s32 igb_set_eee_i354(
struct e1000_hw *,
bool adv1G,
bool adv100M);
269 s32 igb_get_eee_status_i354(
struct e1000_hw *hw,
bool *status);
271 #define E1000_I2C_THERMAL_SENSOR_ADDR 0xF8
272 #define E1000_EMC_INTERNAL_DATA 0x00
273 #define E1000_EMC_INTERNAL_THERM_LIMIT 0x20
274 #define E1000_EMC_DIODE1_DATA 0x01
275 #define E1000_EMC_DIODE1_THERM_LIMIT 0x19
276 #define E1000_EMC_DIODE2_DATA 0x23
277 #define E1000_EMC_DIODE2_THERM_LIMIT 0x1A
278 #define E1000_EMC_DIODE3_DATA 0x2A
279 #define E1000_EMC_DIODE3_THERM_LIMIT 0x30