45 #define RF2525E 0x0204
61 #define SECCSR0 0x0028
101 #define PCICSR 0x008c
107 #define TIMECSR2 0x00a8
110 #define TIMECSR3 0x00b4
118 #define PWRCSR0 0x00c4
119 #define PSCSR0 0x00c8
120 #define PSCSR1 0x00cc
121 #define PSCSR2 0x00d0
122 #define PSCSR3 0x00d4
123 #define PWRCSR1 0x00d8
124 #define TIMECSR 0x00dc
125 #define MACCSR0 0x00e0
126 #define MACCSR1 0x00e4
127 #define RALINKCSR 0x00e8
128 #define BCNCSR 0x00ec
133 #define BBPCSR 0x00f0
135 #define LEDCSR 0x00f8
137 #define SECCSR3 0x00fc
144 #define PRIPTR 0x0108
145 #define ATIMPTR 0x010c
147 #define TXACKCSR0 0x0110
148 #define ACKCNT0 0x0114
149 #define ACKCNT1 0x0118
154 #define GPIOCSR 0x0120
155 #define FIFOCSR0 0x0128
156 #define FIFOCSR1 0x012c
157 #define BCNCSR1 0x0130
158 #define MACCSR2 0x0134
159 #define TESTCSR 0x0138
160 #define ARCSR2 0x013c
161 #define ARCSR3 0x0140
162 #define ARCSR4 0x0144
163 #define ARCSR5 0x0148
164 #define ARTCSR0 0x014c
169 #define SECCSR1 0x0158
170 #define BBPCSR1 0x015c
171 #define DBANDCSR0 0x0160
172 #define DBANDCSR1 0x0164
173 #define BBPPCSR 0x0168
174 #define DBGSEL0 0x016c
175 #define DBGSEL1 0x0170
176 #define BISTCSR 0x0174
177 #define MCAST0 0x0178
178 #define MCAST1 0x017c
179 #define UARTCSR0 0x0180
180 #define UARTCSR1 0x0184
181 #define UARTCSR3 0x0188
182 #define UARTCSR4 0x018c
183 #define UART2CSR0 0x0190
184 #define UART2CSR1 0x0194
185 #define UART2CSR3 0x0198
186 #define UART2CSR4 0x019c
191 #define EEPROM_ANTENNA 0x10
192 #define EEPROM_GEOGRAPHY 0x12
193 #define EEPROM_BBP_START 0x13
194 #define EEPROM_BBP_END 0x22
196 #define EEPROM_BBP_SIZE 16
206 #define CSR1_SOFT_RESET \
207 FIELD32(0, 0x00000001)
208 #define CSR1_BBP_RESET \
209 FIELD32(1, 0x00000002)
210 #define CSR1_HOST_READY \
211 FIELD32(2, 0x00000004)
216 #define CSR3_BYTE0 FIELD32(0, 0x000000ff)
217 #define CSR3_BYTE1 FIELD32(8, 0x0000ff00)
218 #define CSR3_BYTE2 FIELD32(16, 0x00ff0000)
219 #define CSR3_BYTE3 FIELD32(24, 0xff000000)
224 #define CSR4_BYTE4 FIELD32(0, 0x000000ff)
225 #define CSR4_BYTE5 FIELD32(8, 0x0000ff00)
230 #define CSR5_BYTE0 FIELD32(0, 0x000000ff)
231 #define CSR5_BYTE1 FIELD32(8, 0x0000ff00)
232 #define CSR5_BYTE2 FIELD32(16, 0x00ff0000)
233 #define CSR5_BYTE3 FIELD32(24, 0xff000000)
238 #define CSR6_BYTE4 FIELD32(0, 0x000000ff)
239 #define CSR6_BYTE5 FIELD32(8, 0x0000ff00)
245 #define CSR7_TBCN_EXPIRE \
246 FIELD32(0, 0x00000001)
247 #define CSR7_TWAKE_EXPIRE \
248 FIELD32(1, 0x00000002)
249 #define CSR7_TATIMW_EXPIRE \
250 FIELD32(2, 0x00000004)
251 #define CSR7_TXDONE_TXRING \
252 FIELD32(3, 0x00000008)
253 #define CSR7_TXDONE_ATIMRING \
254 FIELD32(4, 0x00000010)
255 #define CSR7_TXDONE_PRIORING \
256 FIELD32(5, 0x00000020)
257 #define CSR7_RXDONE FIELD32(6, 0x00000040)
258 #define CSR7_DECRYPTION_DONE \
259 FIELD32(7, 0x00000080)
260 #define CSR7_ENCRYPTION_DONE \
261 FIELD32(8, 0x00000100)
262 #define CSR7_UART1_TX_TRESHOLD \
263 FIELD32(9, 0x00000200)
264 #define CSR7_UART1_RX_TRESHOLD \
265 FIELD32(10, 0x00000400)
266 #define CSR7_UART1_IDLE_TRESHOLD \
267 FIELD32(11, 0x00000800)
268 #define CSR7_UART1_TX_BUFF_ERROR \
269 FIELD32(12, 0x00001000)
270 #define CSR7_UART1_RX_BUFF_ERROR \
271 FIELD32(13, 0x00002000)
272 #define CSR7_UART2_TX_TRESHOLD \
273 FIELD32(14, 0x00004000)
274 #define CSR7_UART2_RX_TRESHOLD \
275 FIELD32(15, 0x00008000)
276 #define CSR7_UART2_IDLE_TRESHOLD \
277 FIELD32(16, 0x00010000)
278 #define CSR7_UART2_TX_BUFF_ERROR \
279 FIELD32(17, 0x00020000)
280 #define CSR7_UART2_RX_BUFF_ERROR \
281 FIELD32(18, 0x00040000)
282 #define CSR7_TIMER_CSR3_EXPIRE \
290 #define CSR8_TBCN_EXPIRE \
291 FIELD32(0, 0x00000001)
292 #define CSR8_TWAKE_EXPIRE \
293 FIELD32(1, 0x00000002)
294 #define CSR8_TATIMW_EXPIRE \
295 FIELD32(2, 0x00000004)
296 #define CSR8_TXDONE_TXRING \
297 FIELD32(3, 0x00000008)
298 #define CSR8_TXDONE_ATIMRING \
299 FIELD32(4, 0x00000010)
300 #define CSR8_TXDONE_PRIORING \
301 FIELD32(5, 0x00000020)
302 #define CSR8_RXDONE FIELD32(6, 0x00000040)
303 #define CSR8_DECRYPTION_DONE \
304 FIELD32(7, 0x00000080)
305 #define CSR8_ENCRYPTION_DONE \
306 FIELD32(8, 0x00000100)
307 #define CSR8_UART1_TX_TRESHOLD \
308 FIELD32(9, 0x00000200)
309 #define CSR8_UART1_RX_TRESHOLD \
310 FIELD32(10, 0x00000400)
311 #define CSR8_UART1_IDLE_TRESHOLD \
312 FIELD32(11, 0x00000800)
313 #define CSR8_UART1_TX_BUFF_ERROR \
314 FIELD32(12, 0x00001000)
315 #define CSR8_UART1_RX_BUFF_ERROR \
316 FIELD32(13, 0x00002000)
317 #define CSR8_UART2_TX_TRESHOLD \
318 FIELD32(14, 0x00004000)
319 #define CSR8_UART2_RX_TRESHOLD \
320 FIELD32(15, 0x00008000)
321 #define CSR8_UART2_IDLE_TRESHOLD \
322 FIELD32(16, 0x00010000)
323 #define CSR8_UART2_TX_BUFF_ERROR \
324 FIELD32(17, 0x00020000)
325 #define CSR8_UART2_RX_BUFF_ERROR \
326 FIELD32(18, 0x00040000)
327 #define CSR8_TIMER_CSR3_EXPIRE \
334 #define CSR9_MAX_FRAME_UNIT \
341 #define SECCSR0_KICK_DECRYPT \
342 FIELD32(0, 0x00000001)
343 #define SECCSR0_ONE_SHOT \
344 FIELD32(1, 0x00000002)
345 #define SECCSR0_DESC_ADDRESS \
346 FIELD32(2, 0xfffffffc)
351 #define CSR11_CWMIN \
352 FIELD32(0, 0x0000000f)
353 #define CSR11_CWMAX \
354 FIELD32(4, 0x000000f0)
355 #define CSR11_SLOT_TIME \
356 FIELD32(8, 0x00001f00)
357 #define CSR11_CW_SELECT \
360 #define CSR11_LONG_RETRY FIELD32(16, 0x00ff0000)
361 #define CSR11_SHORT_RETRY FIELD32(24, 0xff000000)
367 #define CSR12_BEACON_INTERVAL \
368 FIELD32(0, 0x0000ffff)
369 #define CSR12_CFPMAX_DURATION \
370 FIELD32(16, 0xffff0000)
376 #define CSR13_ATIMW_DURATION FIELD32(0, 0x0000ffff)
377 #define CSR13_CFP_PERIOD \
378 FIELD32(16, 0x00ff0000)
383 #define CSR14_TSF_COUNT FIELD32(0, 0x00000001)
384 #define CSR14_TSF_SYNC \
387 #define CSR14_TBCN FIELD32(3, 0x00000008)
389 FIELD32(4, 0x00000010)
390 #define CSR14_TATIMW \
391 FIELD32(5, 0x00000020)
392 #define CSR14_BEACON_GEN FIELD32(6, 0x00000040)
393 #define CSR14_CFP_COUNT_PRELOAD \
394 FIELD32(8, 0x0000ff00)
395 #define CSR14_TBCM_PRELOAD \
396 FIELD32(16, 0xffff0000)
402 FIELD32(0, 0x00000001)
403 #define CSR15_ATIMW FIELD32(1, 0x00000002)
404 #define CSR15_BEACON_SENT FIELD32(2, 0x00000004)
409 #define CSR16_LOW_TSFTIMER FIELD32(0, 0xffffffff)
414 #define CSR17_HIGH_TSFTIMER FIELD32(0, 0xffffffff)
419 #define CSR18_SIFS FIELD32(0, 0x000001ff)
420 #define CSR18_PIFS FIELD32(16, 0x01f00000)
425 #define CSR19_DIFS FIELD32(0, 0x0000ffff)
426 #define CSR19_EIFS FIELD32(16, 0xffff0000)
431 #define CSR20_DELAY_AFTER_TBCN \
434 #define CSR20_TBCN_BEFORE_WAKEUP \
435 FIELD32(16, 0x00ff0000)
436 #define CSR20_AUTOWAKE \
437 FIELD32(24, 0x01000000)
442 #define CSR21_RELOAD \
443 FIELD32(0, 0x00000001)
444 #define CSR21_EEPROM_DATA_CLOCK FIELD32(1, 0x00000002)
445 #define CSR21_EEPROM_CHIP_SELECT FIELD32(2, 0x00000004)
446 #define CSR21_EEPROM_DATA_IN FIELD32(3, 0x00000008)
447 #define CSR21_EEPROM_DATA_OUT FIELD32(4, 0x00000010)
448 #define CSR21_TYPE_93C46 FIELD32(5, 0x00000020)
453 #define CSR22_CFP_DURATION_REMAIN \
454 FIELD32(0, 0x0000ffff)
455 #define CSR22_RELOAD_CFP_DURATION \
456 FIELD32(16, 0x00010000)
466 #define TXCSR0_KICK_TX FIELD32(0, 0x00000001)
467 #define TXCSR0_KICK_ATIM FIELD32(1, 0x00000002)
468 #define TXCSR0_KICK_PRIO FIELD32(2, 0x00000004)
469 #define TXCSR0_ABORT \
470 FIELD32(3, 0x00000008)
475 #define TXCSR1_ACK_TIMEOUT \
478 #define TXCSR1_ACK_CONSUME_TIME \
481 #define TXCSR1_TSF_OFFSET FIELD32(18, 0x00fc0000)
482 #define TXCSR1_AUTORESPONDER \
489 #define TXCSR2_TXD_SIZE \
490 FIELD32(0, 0x000000ff)
491 #define TXCSR2_NUM_TXD FIELD32(8, 0x0000ff00)
492 #define TXCSR2_NUM_ATIM FIELD32(16, 0x00ff0000)
493 #define TXCSR2_NUM_PRIO \
494 FIELD32(24, 0xff000000)
499 #define TXCSR3_TX_RING_REGISTER FIELD32(0, 0xffffffff)
504 #define TXCSR4_ATIM_RING_REGISTER FIELD32(0, 0xffffffff)
509 #define TXCSR5_PRIO_RING_REGISTER FIELD32(0, 0xffffffff)
514 #define TXCSR6_BEACON_REGISTER FIELD32(0, 0xffffffff)
519 #define TXCSR7_AR_POWERMANAGEMENT \
520 FIELD32(0, 0x00000001)
525 #define TXCSR8_CCK_SIGNAL \
526 FIELD32(0, 0x000000ff)
527 #define TXCSR8_CCK_SERVICE \
528 FIELD32(8, 0x0000ff00)
529 #define TXCSR8_CCK_LENGTH_LOW \
530 FIELD32(16, 0x00ff0000)
531 #define TXCSR8_CCK_LENGTH_HIGH \
532 FIELD32(24, 0xff000000)
537 #define TXCSR9_OFDM_RATE \
538 FIELD32(0, 0x000000ff)
539 #define TXCSR9_OFDM_SERVICE \
540 FIELD32(8, 0x0000ff00)
541 #define TXCSR9_OFDM_LENGTH_LOW \
542 FIELD32(16, 0x00ff0000)
543 #define TXCSR9_OFDM_LENGTH_HIGH \
544 FIELD32(24, 0xff000000)
549 #define RXCSR0_DISABLE_RX FIELD32(0, 0x00000001)
550 #define RXCSR0_DROP_CRC FIELD32(1, 0x00000002)
551 #define RXCSR0_DROP_PHYSICAL FIELD32(2, 0x00000004)
552 #define RXCSR0_DROP_CONTROL FIELD32(3, 0x00000008)
553 #define RXCSR0_DROP_NOT_TO_ME \
554 FIELD32(4, 0x00000010)
555 #define RXCSR0_DROP_TODS \
556 FIELD32(5, 0x00000020)
557 #define RXCSR0_DROP_VERSION_ERROR \
558 FIELD32(6, 0x00000040)
559 #define RXCSR0_PASS_CRC \
560 FIELD32(7, 0x00000080)
561 #define RXCSR0_PASS_PLCP \
564 #define RXCSR0_DROP_MCAST FIELD32(9, 0x00000200)
565 #define RXCSR0_DROP_BCAST FIELD32(10, 0x00000400)
566 #define RXCSR0_ENABLE_QOS \
567 FIELD32(11, 0x00000800)
572 #define RXCSR1_RXD_SIZE \
573 FIELD32(0, 0x000000ff)
574 #define RXCSR1_NUM_RXD FIELD32(8, 0x0000ff00)
579 #define RXCSR2_RX_RING_REGISTER FIELD32(0, 0xffffffff)
584 #define RXCSR3_BBP_ID0 FIELD32(0, 0x0000007f)
585 #define RXCSR3_BBP_ID0_VALID \
586 FIELD32(7, 0x00000080)
587 #define RXCSR3_BBP_ID1 FIELD32(8, 0x00007f00)
588 #define RXCSR3_BBP_ID1_VALID \
589 FIELD32(15, 0x00008000)
590 #define RXCSR3_BBP_ID2 FIELD32(16, 0x007f0000)
591 #define RXCSR3_BBP_ID2_VALID \
592 FIELD32(23, 0x00800000)
593 #define RXCSR3_BBP_ID3 FIELD32(24, 0x7f000000)
594 #define RXCSR3_BBP_ID3_VALID \
595 FIELD32(31, 0x80000000)
600 #define ARCSR1_AR_BBP_DATA2 \
601 FIELD32(0, 0x000000ff)
602 #define ARCSR1_AR_BBP_ID2 \
603 FIELD32(8, 0x0000ff00)
604 #define ARCSR1_AR_BBP_DATA3 \
605 FIELD32(16, 0x00ff0000)
606 #define ARCSR1_AR_BBP_ID3 \
607 FIELD32(24, 0xff000000)
617 #define PCICSR_BIG_ENDIAN \
618 FIELD32(0, 0x00000001)
619 #define PCICSR_RX_TRESHOLD \
620 FIELD32(1, 0x00000006)
622 #define PCICSR_TX_TRESHOLD \
623 FIELD32(3, 0x00000018)
625 #define PCICSR_BURST_LENTH FIELD32(5, 0x00000060)
627 #define PCICSR_ENABLE_CLK FIELD32(7, 0x00000080)
629 #define PCICSR_READ_MULTIPLE \
630 FIELD32(8, 0x00000100)
631 #define PCICSR_WRITE_INVALID \
632 FIELD32(9, 0x00000200)
638 #define PWRCSR1_SET_STATE \
641 #define PWRCSR1_BBP_DESIRE_STATE FIELD32(1, 0x00000006)
642 #define PWRCSR1_RF_DESIRE_STATE FIELD32(3, 0x00000018)
643 #define PWRCSR1_BBP_CURR_STATE FIELD32(5, 0x00000060)
644 #define PWRCSR1_RF_CURR_STATE FIELD32(7, 0x00000180)
645 #define PWRCSR1_PUT_TO_SLEEP \
652 #define TIMECSR_US_COUNT \
653 FIELD32(0, 0x000000ff)
654 #define TIMECSR_US_64_COUNT \
655 FIELD32(8, 0x0000ff00)
656 #define TIMECSR_BEACON_EXPECT \
657 FIELD32(16, 0x00070000)
662 #define MACCSR1_KICK_RX \
663 FIELD32(0, 0x00000001)
664 #define MACCSR1_ONESHOT_RXMODE \
665 FIELD32(1, 0x00000002)
666 #define MACCSR1_BBPRX_RESET_MODE \
667 FIELD32(2, 0x00000004)
668 #define MACCSR1_AUTO_TXBBP \
669 FIELD32(3, 0x00000008)
670 #define MACCSR1_AUTO_RXBBP \
671 FIELD32(4, 0x00000010)
672 #define MACCSR1_LOOPBACK FIELD32(5, 0x00000060)
674 #define MACCSR1_INTERSIL_IF \
675 FIELD32(7, 0x00000080)
680 #define RALINKCSR_AR_BBP_DATA0 \
681 FIELD32(0, 0x000000ff)
682 #define RALINKCSR_AR_BBP_ID0 \
683 FIELD32(8, 0x00007f00)
684 #define RALINKCSR_AR_BBP_VALID0 \
685 FIELD32(15, 0x00008000)
686 #define RALINKCSR_AR_BBP_DATA1 \
687 FIELD32(16, 0x00ff0000)
688 #define RALINKCSR_AR_BBP_ID1 \
689 FIELD32(24, 0x7f000000)
690 #define RALINKCSR_AR_BBP_VALID1 \
691 FIELD32(31, 0x80000000)
696 #define BCNCSR_CHANGE \
697 FIELD32(0, 0x00000001)
698 #define BCNCSR_DELTATIME FIELD32(1, 0x0000001e)
699 #define BCNCSR_NUM_BEACON \
700 FIELD32(5, 0x00001fe0)
701 #define BCNCSR_MODE FIELD32(13, 0x00006000)
702 #define BCNCSR_PLUS \
703 FIELD32(15, 0x00008000)
708 #define BBPCSR_VALUE \
709 FIELD32(0, 0x000000ff)
710 #define BBPCSR_REGNUM FIELD32(8, 0x00007f00)
711 #define BBPCSR_BUSY \
712 FIELD32(15, 0x00008000)
713 #define BBPCSR_WRITE_CONTROL \
714 FIELD32(16, 0x00010000)
719 #define RFCSR_VALUE \
720 FIELD32(0, 0x00ffffff)
721 #define RFCSR_NUMBER_OF_BITS \
724 #define RFCSR_IF_SELECT \
725 FIELD32(29, 0x20000000)
726 #define RFCSR_PLL_LD FIELD32(30, 0x40000000)
728 FIELD32(31, 0x80000000)
733 #define LEDCSR_ON_PERIOD FIELD32(0, 0x000000ff)
734 #define LEDCSR_OFF_PERIOD FIELD32(8, 0x0000ff00)
735 #define LEDCSR_LINK FIELD32(16, 0x00010000)
736 #define LEDCSR_ACTIVITY FIELD32(17, 0x00020000)
737 #define LEDCSR_LINK_POLARITY \
738 FIELD32(18, 0x00040000)
739 #define LEDCSR_ACTIVITY_POLARITY \
740 FIELD32(19, 0x00080000)
741 #define LEDCSR_LED_DEFAULT \
742 FIELD32(20, 0x00100000)
747 #define GPIOCSR_BIT0 FIELD32(0, 0x00000001)
748 #define GPIOCSR_BIT1 FIELD32(1, 0x00000002)
749 #define GPIOCSR_BIT2 FIELD32(2, 0x00000004)
750 #define GPIOCSR_BIT3 FIELD32(3, 0x00000008)
751 #define GPIOCSR_BIT4 FIELD32(4, 0x00000010)
752 #define GPIOCSR_BIT5 FIELD32(5, 0x00000020)
753 #define GPIOCSR_BIT6 FIELD32(6, 0x00000040)
754 #define GPIOCSR_BIT7 FIELD32(7, 0x00000080)
755 #define GPIOCSR_DIR0 FIELD32(8, 0x00000100)
756 #define GPIOCSR_DIR1 FIELD32(9, 0x00000200)
757 #define GPIOCSR_DIR2 FIELD32(10, 0x00000400)
758 #define GPIOCSR_DIR3 FIELD32(11, 0x00000800)
759 #define GPIOCSR_DIR4 FIELD32(12, 0x00001000)
760 #define GPIOCSR_DIR5 FIELD32(13, 0x00002000)
761 #define GPIOCSR_DIR6 FIELD32(14, 0x00004000)
762 #define GPIOCSR_DIR7 FIELD32(15, 0x00008000)
767 #define BCNCSR1_PRELOAD \
768 FIELD32(0, 0x0000ffff)
769 #define BCNCSR1_BEACON_CWMIN FIELD32(16, 0x000f0000)
774 #define MACCSR2_DELAY \
781 #define SECCSR1_KICK_ENCRYPT \
782 FIELD32(0, 0x00000001)
783 #define SECCSR1_ONE_SHOT \
784 FIELD32(1, 0x00000002)
785 #define SECCSR1_DESC_ADDRESS \
786 FIELD32(2, 0xfffffffc)
791 #define RF1_TUNER FIELD32(17, 0x00020000)
792 #define RF3_TUNER FIELD32(8, 0x00000100)
793 #define RF3_TXPOWER FIELD32(9, 0x00003e00)
803 #define EEPROM_WIDTH_93c46 6
804 #define EEPROM_WIDTH_93c66 8
805 #define EEPROM_WRITE_OPCODE 0x05
806 #define EEPROM_READ_OPCODE 0x06
811 #define EEPROM_ANTENNA_NUM FIELD16(0, 0x0003)
812 #define EEPROM_ANTENNA_TX_DEFAULT \
814 #define EEPROM_ANTENNA_RX_DEFAULT \
816 #define EEPROM_ANTENNA_LED_MODE \
819 #define EEPROM_ANTENNA_DYN_TXAGC \
821 #define EEPROM_ANTENNA_HARDWARE_RADIO \
823 #define EEPROM_ANTENNA_RF_TYPE \
829 #define EEPROM_GEOGRAPHY_GEO \
835 #define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0, 0x0001)
836 #define EEPROM_NIC_DYN_BBP_TUNE FIELD16(1, 0x0002)
837 #define EEPROM_NIC_CCK_TX_POWER \
843 #define EEPROM_TX_POWER1 FIELD16(0, 0x00ff)
844 #define EEPROM_TX_POWER2 FIELD16(8, 0xff00)
849 #define EEPROM_BBP_VALUE FIELD16(0, 0x00ff)
850 #define EEPROM_BBP_REG_ID FIELD16(8, 0xff00)
855 #define EEPROM_VERSION_FAE FIELD16(0, 0x00ff)
856 #define EEPROM_VERSION FIELD16(8, 0xff00)
865 #define SIZE_DESCRIPTOR 48
872 #define TXD_W0_OWNER_NIC FIELD32(0, 0x00000001)
873 #define TXD_W0_VALID FIELD32(1, 0x00000002)
874 #define TXD_W0_RESULT FIELD32(2, 0x0000001c)
875 #define TXD_W0_RETRY_COUNT FIELD32(5, 0x000000e0)
876 #define TXD_W0_MORE_FRAG FIELD32(8, 0x00000100)
877 #define TXD_W0_ACK FIELD32(9, 0x00000200)
878 #define TXD_W0_TIMESTAMP FIELD32(10, 0x00000400)
879 #define TXD_W0_OFDM FIELD32(11, 0x00000800)
880 #define TXD_W0_CIPHER_OWNER FIELD32(12, 0x00001000)
881 #define TXD_W0_IFS FIELD32(13, 0x00006000)
882 #define TXD_W0_RETRY_MODE FIELD32(15, 0x00008000)
883 #define TXD_W0_DATABYTE_COUNT FIELD32(16, 0x0fff0000)
884 #define TXD_W0_CIPHER_ALG FIELD32(29, 0xe0000000)
887 #define TXD_W1_BUFFER_ADDRESS FIELD32(0, 0xffffffff)
890 #define TXD_W2_IV_OFFSET FIELD32(0, 0x0000003f)
891 #define TXD_W2_AIFS FIELD32(6, 0x000000c0)
892 #define TXD_W2_CWMIN FIELD32(8, 0x00000f00)
893 #define TXD_W2_CWMAX FIELD32(12, 0x0000f000)
896 #define TXD_W3_PLCP_SIGNAL FIELD32(0, 0x000000ff)
897 #define TXD_W3_PLCP_SERVICE FIELD32(8, 0x0000ff00)
898 #define TXD_W3_PLCP_LENGTH_LOW FIELD32(16, 0x00ff0000)
899 #define TXD_W3_PLCP_LENGTH_HIGH FIELD32(24, 0xff000000)
902 #define TXD_W4_IV FIELD32(0, 0xffffffff)
905 #define TXD_W5_EIV FIELD32(0, 0xffffffff)
908 #define TXD_W6_KEY FIELD32(0, 0xffffffff)
911 #define TXD_W7_KEY FIELD32(0, 0xffffffff)
914 #define TXD_W8_KEY FIELD32(0, 0xffffffff)
917 #define TXD_W9_KEY FIELD32(0, 0xffffffff)
920 #define TXD_W10_RTS FIELD32(0, 0x00000001)
921 #define TXD_W10_TX_RATE FIELD32(0, 0x000000fe)
929 #define RXD_W0_OWNER_NIC FIELD32(0, 0x00000001)
930 #define RXD_W0_UNICAST_TO_ME FIELD32(1, 0x00000002)
931 #define RXD_W0_MULTICAST FIELD32(2, 0x00000004)
932 #define RXD_W0_BROADCAST FIELD32(3, 0x00000008)
933 #define RXD_W0_MY_BSS FIELD32(4, 0x00000010)
934 #define RXD_W0_CRC FIELD32(5, 0x00000020)
935 #define RXD_W0_OFDM FIELD32(6, 0x00000040)
936 #define RXD_W0_PHYSICAL_ERROR FIELD32(7, 0x00000080)
937 #define RXD_W0_CIPHER_OWNER FIELD32(8, 0x00000100)
938 #define RXD_W0_ICV_ERROR FIELD32(9, 0x00000200)
939 #define RXD_W0_IV_OFFSET FIELD32(10, 0x0000fc00)
940 #define RXD_W0_DATABYTE_COUNT FIELD32(16, 0x0fff0000)
941 #define RXD_W0_CIPHER_ALG FIELD32(29, 0xe0000000)
944 #define RXD_W1_BUFFER_ADDRESS FIELD32(0, 0xffffffff)
947 #define RXD_W2_BBR0 FIELD32(0, 0x000000ff)
948 #define RXD_W2_RSSI FIELD32(8, 0x0000ff00)
949 #define RXD_W2_TA FIELD32(16, 0xffff0000)
952 #define RXD_W3_TA FIELD32(0, 0xffffffff)
955 #define RXD_W4_IV FIELD32(0, 0xffffffff)
958 #define RXD_W5_EIV FIELD32(0, 0xffffffff)
961 #define RXD_W6_KEY FIELD32(0, 0xffffffff)
964 #define RXD_W7_KEY FIELD32(0, 0xffffffff)
967 #define RXD_W8_KEY FIELD32(0, 0xffffffff)
970 #define RXD_W9_KEY FIELD32(0, 0xffffffff)
973 #define RXD_W10_DROP FIELD32(0, 0x00000001)
984 struct pci_dev *pci_dev;
989 struct _rt2x00_chip chip;
995 void __iomem *csr_addr;
1000 struct _rf_channel channel;
1012 u16 eeprom[EEPROM_BBP_SIZE];
1017 struct _data_ring rx;
1018 struct _data_ring tx;
1020 rtdm_irq_t irq_handle;
1025 static int rt2x00_get_rf_value(
const struct _rt2x00_chip *chip,
1026 const u8 channel,
struct _rf_channel *rf_reg)
1030 index = rt2x00_get_channel_index(channel);
1034 memset(rf_reg, 0x00,
sizeof(*rf_reg));
1036 if (rt2x00_rf(chip, RF2522)) {
1037 rf_reg->rf1 = 0x00002050;
1038 rf_reg->rf3 = 0x00000101;
1041 if (rt2x00_rf(chip, RF2523)) {
1042 rf_reg->rf1 = 0x00022010;
1043 rf_reg->rf3 = 0x000e0111;
1044 rf_reg->rf4 = 0x00000a1b;
1047 if (rt2x00_rf(chip, RF2524)) {
1048 rf_reg->rf1 = 0x00032020;
1049 rf_reg->rf3 = 0x00000101;
1050 rf_reg->rf4 = 0x00000a1b;
1053 if (rt2x00_rf(chip, RF2525)) {
1054 rf_reg->rf1 = 0x00022020;
1055 rf_reg->rf2 = 0x00080000;
1056 rf_reg->rf3 = 0x00060111;
1057 rf_reg->rf4 = 0x00000a1b;
1060 if (rt2x00_rf(chip, RF2525E)) {
1061 rf_reg->rf2 = 0x00080000;
1062 rf_reg->rf3 = 0x00060111;
1065 if (rt2x00_rf(chip, RF5222)) {
1066 rf_reg->rf3 = 0x00000101;
1073 rf_reg->rf2 = 0x000c1fda + (index * 0x14);
1075 rf_reg->rf2 += 0x0000001c;
1079 rf_reg->rf2 |= 0x00000c9e + (index * 0x04);
1080 if (rf_reg->rf2 & 0x00000040)
1081 rf_reg->rf2 += 0x00000040;
1082 if (channel == 14) {
1083 rf_reg->rf2 += 0x08;
1084 rf_reg->rf4 &= ~0x00000018;
1089 if (OFDM_CHANNEL(channel)) {
1090 rf_reg->rf1 = 0x00022020;
1091 rf_reg->rf2 |= 0x00001136 + (index * 0x04);
1092 if (rf_reg->rf2 & 0x00000040)
1093 rf_reg->rf2 += 0x00000040;
1094 if (channel == 14) {
1095 rf_reg->rf2 += 0x04;
1096 rf_reg->rf4 = 0x00000a1b;
1098 rf_reg->rf4 = 0x00000a0b;
1100 }
else if (UNII_LOW_CHANNEL(channel)) {
1101 rf_reg->rf1 = 0x00022010;
1102 rf_reg->rf2 = 0x00018896 + (index * 0x04);
1103 rf_reg->rf4 = 0x00000a1f;
1104 }
else if (HIPERLAN2_CHANNEL(channel)) {
1105 rf_reg->rf1 = 0x00022010;
1106 rf_reg->rf2 = 0x00008802 + (index * 0x04);
1107 rf_reg->rf4 = 0x00000a0f;
1108 }
else if (UNII_HIGH_CHANNEL(channel)) {
1109 rf_reg->rf1 = 0x00022020;
1110 rf_reg->rf2 = 0x000090a6 + (index * 0x08);
1111 rf_reg->rf4 = 0x00000a07;
1115 rf_reg->rf1 = cpu_to_le32(rf_reg->rf1);
1116 rf_reg->rf2 = cpu_to_le32(rf_reg->rf2);
1117 rf_reg->rf3 = cpu_to_le32(rf_reg->rf3);
1118 rf_reg->rf4 = cpu_to_le32(rf_reg->rf4);
1126 static inline u8 rt2x00_get_txpower(
const struct _rt2x00_chip *chip,
1129 return tx_power / 100 * 31;
1154 rt2x00_pci_alloc_ring(
struct _rt2x00_core *core,
struct _data_ring *ring,
1155 const u8 ring_type,
const u16 max_entries,
1156 const u16 entry_size,
const u16 desc_size)
1158 struct _rt2x00_pci *rt2x00pci = rt2x00_priv(core);
1160 rt2x00_init_ring(core, ring, ring_type, max_entries, entry_size,
1164 dma_alloc_coherent(&rt2x00pci->pci_dev->dev, ring->mem_size,
1165 &ring->data_dma, GFP_KERNEL);
1166 if (!ring->data_addr)
1169 memset(ring->data_addr, 0x00, ring->mem_size);
1174 static int rt2x00_pci_alloc_rings(
struct _rt2x00_core *core)
1176 struct _rt2x00_pci *rt2x00pci = rt2x00_priv(core);
1178 if (rt2x00_pci_alloc_ring(core, &rt2x00pci->rx, RING_RX, RX_ENTRIES,
1179 DATA_FRAME_SIZE, SIZE_DESCRIPTOR) ||
1180 rt2x00_pci_alloc_ring(core, &rt2x00pci->tx, RING_TX, TX_ENTRIES,
1181 DATA_FRAME_SIZE, SIZE_DESCRIPTOR)) {
1182 ERROR(
"DMA allocation failed.\n");
1189 static inline void rt2x00_pci_free_ring(
struct _data_ring *ring)
1191 struct _rt2x00_pci *rt2x00pci = rt2x00_priv(ring->core);
1193 if (ring->data_addr)
1194 dma_free_coherent(&rt2x00pci->pci_dev->dev, ring->mem_size,
1195 ring->data_addr, ring->data_dma);
1196 ring->data_addr = NULL;
1198 rt2x00_deinit_ring(ring);
1201 static void rt2x00_pci_free_rings(
struct _rt2x00_core *core)
1203 struct _rt2x00_pci *rt2x00pci = rt2x00_priv(core);
1205 rt2x00_pci_free_ring(&rt2x00pci->rx);
1206 rt2x00_pci_free_ring(&rt2x00pci->tx);
1212 #define DESC_BASE(__ring) ((void *)((__ring)->data_addr))
1213 #define DATA_BASE(__ring) \
1214 ((void *)(DESC_BASE(__ring) + \
1215 ((__ring)->max_entries * (__ring)->desc_size)))
1217 #define __DESC_ADDR(__ring, __index) \
1218 ((void *)(DESC_BASE(__ring) + ((__index) * (__ring)->desc_size)))
1219 #define __DATA_ADDR(__ring, __index) \
1220 ((void *)(DATA_BASE(__ring) + ((__index) * (__ring)->entry_size)))
1222 #define DESC_ADDR(__ring) (__DESC_ADDR(__ring, (__ring)->index))
1223 #define DESC_ADDR_DONE(__ring) (__DESC_ADDR(__ring, (__ring)->index_done))
1225 #define DATA_ADDR(__ring) (__DATA_ADDR(__ring, (__ring)->index))
1226 #define DATA_ADDR_DONE(__ring) (__DATA_ADDR(__ring, (__ring)->index_done))
1236 #define REGISTER_BUSY_COUNT \
1238 #define REGISTER_BUSY_DELAY \
1241 static void rt2x00_register_read(
const struct _rt2x00_pci *rt2x00pci,
1242 const unsigned long offset, u32 *value)
1244 *value = readl((
void *)(rt2x00pci->csr_addr + offset));
1247 static void rt2x00_register_multiread(
const struct _rt2x00_pci *rt2x00pci,
1248 const unsigned long offset, u32 *value,
1251 memcpy_fromio((
void *)value, (
void *)(rt2x00pci->csr_addr + offset),
1255 static void rt2x00_register_write(
const struct _rt2x00_pci *rt2x00pci,
1256 const unsigned long offset,
const u32 value)
1258 writel(value, (
void *)(rt2x00pci->csr_addr + offset));
1261 static void rt2x00_register_multiwrite(
const struct _rt2x00_pci *rt2x00pci,
1262 const unsigned long offset, u32 *value,
1265 memcpy_toio((
void *)(rt2x00pci->csr_addr + offset), (
void *)value,
1269 static void rt2x00_bbp_regwrite(
const struct _rt2x00_pci *rt2x00pci,
1270 const u8 reg_id,
const u8 value)
1272 u32 reg = 0x00000000;
1275 for (counter = 0x00; counter < REGISTER_BUSY_COUNT; counter++) {
1276 rt2x00_register_read(rt2x00pci, BBPCSR, ®);
1277 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
1279 udelay(REGISTER_BUSY_DELAY);
1282 ERROR(
"BBPCSR register busy. Write failed\n");
1287 rt2x00_set_field32(®, BBPCSR_VALUE, value);
1288 rt2x00_set_field32(®, BBPCSR_REGNUM, reg_id);
1289 rt2x00_set_field32(®, BBPCSR_BUSY, 1);
1290 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 1);
1292 rt2x00_register_write(rt2x00pci, BBPCSR, reg);
1295 static void rt2x00_bbp_regread(
const struct _rt2x00_pci *rt2x00pci,
1296 const u8 reg_id, u8 *value)
1298 u32 reg = 0x00000000;
1305 rt2x00_set_field32(®, BBPCSR_REGNUM, reg_id);
1306 rt2x00_set_field32(®, BBPCSR_BUSY, 1);
1307 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 0);
1309 rt2x00_register_write(rt2x00pci, BBPCSR, reg);
1311 for (counter = 0x00; counter < REGISTER_BUSY_COUNT; counter++) {
1312 rt2x00_register_read(rt2x00pci, BBPCSR, ®);
1313 if (!rt2x00_get_field32(reg, BBPCSR_BUSY)) {
1314 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
1317 udelay(REGISTER_BUSY_DELAY);
1320 ERROR(
"BBPCSR register busy. Read failed\n");
1324 static void rt2x00_rf_regwrite(
const struct _rt2x00_pci *rt2x00pci,
1327 u32 reg = 0x00000000;
1330 for (counter = 0x00; counter < REGISTER_BUSY_COUNT; counter++) {
1331 rt2x00_register_read(rt2x00pci, RFCSR, ®);
1332 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
1334 udelay(REGISTER_BUSY_DELAY);
1337 ERROR(
"RFCSR register busy. Write failed\n");
1342 rt2x00_set_field32(®, RFCSR_NUMBER_OF_BITS, 20);
1343 rt2x00_set_field32(®, RFCSR_IF_SELECT, 0);
1344 rt2x00_set_field32(®, RFCSR_BUSY, 1);
1348 rt2x00_register_write(rt2x00pci, RFCSR, reg);
1358 static inline void rt2x00_eeprom_pulse_high(
const struct _rt2x00_pci *rt2x00pci,
1361 rt2x00_set_field32(flags, CSR21_EEPROM_DATA_CLOCK, 1);
1362 rt2x00_register_write(rt2x00pci, CSR21, *flags);
1366 static inline void rt2x00_eeprom_pulse_low(
const struct _rt2x00_pci *rt2x00pci,
1369 rt2x00_set_field32(flags, CSR21_EEPROM_DATA_CLOCK, 0);
1370 rt2x00_register_write(rt2x00pci, CSR21, *flags);
1374 static void rt2x00_eeprom_shift_out_bits(
const struct _rt2x00_pci *rt2x00pci,
1375 const u16 data,
const u16 count)
1377 u32 flags = 0x00000000;
1378 u32 mask = 0x0001 << (count - 1);
1380 rt2x00_register_read(rt2x00pci, CSR21, &flags);
1385 rt2x00_set_field32(&flags, CSR21_EEPROM_DATA_IN, 0);
1386 rt2x00_set_field32(&flags, CSR21_EEPROM_DATA_OUT, 0);
1395 rt2x00_set_field32(&flags, CSR21_EEPROM_DATA_IN,
1396 (data & mask) ? 1 : 0);
1398 rt2x00_register_write(rt2x00pci, CSR21, flags);
1400 rt2x00_eeprom_pulse_high(rt2x00pci, &flags);
1401 rt2x00_eeprom_pulse_low(rt2x00pci, &flags);
1409 rt2x00_set_field32(&flags, CSR21_EEPROM_DATA_IN, 0);
1410 rt2x00_register_write(rt2x00pci, CSR21, flags);
1413 static void rt2x00_eeprom_shift_in_bits(
const struct _rt2x00_pci *rt2x00pci,
1416 u32 flags = 0x00000000;
1419 rt2x00_register_read(rt2x00pci, CSR21, &flags);
1424 rt2x00_set_field32(&flags, CSR21_EEPROM_DATA_IN, 0);
1425 rt2x00_set_field32(&flags, CSR21_EEPROM_DATA_OUT, 0);
1430 for (counter = 0; counter < 16; counter++) {
1436 rt2x00_eeprom_pulse_high(rt2x00pci, &flags);
1438 rt2x00_register_read(rt2x00pci, CSR21, &flags);
1443 rt2x00_set_field32(&flags, CSR21_EEPROM_DATA_IN, 0);
1444 if (rt2x00_get_field32(flags, CSR21_EEPROM_DATA_OUT))
1447 rt2x00_eeprom_pulse_low(rt2x00pci, &flags);
1451 static u16 rt2x00_eeprom_read_word(
const struct _rt2x00_pci *rt2x00pci,
1454 u32 flags = 0x00000000;
1460 rt2x00_register_read(rt2x00pci, CSR21, &flags);
1461 rt2x00_set_field32(&flags, CSR21_EEPROM_DATA_IN, 0);
1462 rt2x00_set_field32(&flags, CSR21_EEPROM_DATA_OUT, 0);
1463 rt2x00_set_field32(&flags, CSR21_EEPROM_DATA_CLOCK, 0);
1464 rt2x00_set_field32(&flags, CSR21_EEPROM_CHIP_SELECT, 1);
1465 rt2x00_register_write(rt2x00pci, CSR21, flags);
1470 rt2x00_eeprom_pulse_high(rt2x00pci, &flags);
1471 rt2x00_eeprom_pulse_low(rt2x00pci, &flags);
1476 rt2x00_eeprom_shift_out_bits(rt2x00pci, EEPROM_READ_OPCODE, 3);
1477 rt2x00_eeprom_shift_out_bits(rt2x00pci, word, rt2x00pci->eeprom_width);
1479 rt2x00_eeprom_shift_in_bits(rt2x00pci, &data);
1484 rt2x00_register_read(rt2x00pci, CSR21, &flags);
1485 rt2x00_set_field32(&flags, CSR21_EEPROM_DATA_IN, 0);
1486 rt2x00_set_field32(&flags, CSR21_EEPROM_CHIP_SELECT, 0);
1487 rt2x00_register_write(rt2x00pci, CSR21, flags);
1492 rt2x00_eeprom_pulse_high(rt2x00pci, &flags);
1493 rt2x00_eeprom_pulse_low(rt2x00pci, &flags);
static int __attribute__((cold))
Test if a mutex structure contains a valid autoinitializer.
Definition: mutex.c:176
ipipe_spinlock_t rtdm_lock_t
Lock variable.
Definition: driver.h:550