32 #include "e1000_osdep.h"
33 #include "e1000_regs.h"
34 #include "e1000_defines.h"
38 #define E1000_DEV_ID_82542 0x1000
39 #define E1000_DEV_ID_82543GC_FIBER 0x1001
40 #define E1000_DEV_ID_82543GC_COPPER 0x1004
41 #define E1000_DEV_ID_82544EI_COPPER 0x1008
42 #define E1000_DEV_ID_82544EI_FIBER 0x1009
43 #define E1000_DEV_ID_82544GC_COPPER 0x100C
44 #define E1000_DEV_ID_82544GC_LOM 0x100D
45 #define E1000_DEV_ID_82540EM 0x100E
46 #define E1000_DEV_ID_82540EM_LOM 0x1015
47 #define E1000_DEV_ID_82540EP_LOM 0x1016
48 #define E1000_DEV_ID_82540EP 0x1017
49 #define E1000_DEV_ID_82540EP_LP 0x101E
50 #define E1000_DEV_ID_82545EM_COPPER 0x100F
51 #define E1000_DEV_ID_82545EM_FIBER 0x1011
52 #define E1000_DEV_ID_82545GM_COPPER 0x1026
53 #define E1000_DEV_ID_82545GM_FIBER 0x1027
54 #define E1000_DEV_ID_82545GM_SERDES 0x1028
55 #define E1000_DEV_ID_82546EB_COPPER 0x1010
56 #define E1000_DEV_ID_82546EB_FIBER 0x1012
57 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
58 #define E1000_DEV_ID_82546GB_COPPER 0x1079
59 #define E1000_DEV_ID_82546GB_FIBER 0x107A
60 #define E1000_DEV_ID_82546GB_SERDES 0x107B
61 #define E1000_DEV_ID_82546GB_PCIE 0x108A
62 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
63 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
64 #define E1000_DEV_ID_82541EI 0x1013
65 #define E1000_DEV_ID_82541EI_MOBILE 0x1018
66 #define E1000_DEV_ID_82541ER_LOM 0x1014
67 #define E1000_DEV_ID_82541ER 0x1078
68 #define E1000_DEV_ID_82541GI 0x1076
69 #define E1000_DEV_ID_82541GI_LF 0x107C
70 #define E1000_DEV_ID_82541GI_MOBILE 0x1077
71 #define E1000_DEV_ID_82547EI 0x1019
72 #define E1000_DEV_ID_82547EI_MOBILE 0x101A
73 #define E1000_DEV_ID_82547GI 0x1075
74 #define E1000_DEV_ID_82571EB_COPPER 0x105E
75 #define E1000_DEV_ID_82571EB_FIBER 0x105F
76 #define E1000_DEV_ID_82571EB_SERDES 0x1060
77 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
78 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
79 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
80 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
81 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
82 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
83 #define E1000_DEV_ID_82572EI_COPPER 0x107D
84 #define E1000_DEV_ID_82572EI_FIBER 0x107E
85 #define E1000_DEV_ID_82572EI_SERDES 0x107F
86 #define E1000_DEV_ID_82572EI 0x10B9
87 #define E1000_DEV_ID_82573E 0x108B
88 #define E1000_DEV_ID_82573E_IAMT 0x108C
89 #define E1000_DEV_ID_82573L 0x109A
90 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
91 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
92 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
93 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
94 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
95 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
96 #define E1000_DEV_ID_ICH8_IGP_C 0x104B
97 #define E1000_DEV_ID_ICH8_IFE 0x104C
98 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
99 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5
100 #define E1000_DEV_ID_ICH8_IGP_M 0x104D
101 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
102 #define E1000_DEV_ID_ICH9_IGP_C 0x294C
103 #define E1000_DEV_ID_ICH9_IFE 0x10C0
104 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
105 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2
107 #define E1000_REVISION_0 0
108 #define E1000_REVISION_1 1
109 #define E1000_REVISION_2 2
110 #define E1000_REVISION_3 3
111 #define E1000_REVISION_4 4
113 #define E1000_FUNC_0 0
114 #define E1000_FUNC_1 1
140 e1000_media_type_unknown = 0,
141 e1000_media_type_copper = 1,
142 e1000_media_type_fiber = 2,
143 e1000_media_type_internal_serdes = 3,
144 e1000_num_media_types
148 e1000_nvm_unknown = 0,
150 e1000_nvm_eeprom_spi,
151 e1000_nvm_eeprom_microwire,
157 e1000_nvm_override_none = 0,
158 e1000_nvm_override_spi_small,
159 e1000_nvm_override_spi_large,
160 e1000_nvm_override_microwire_small,
161 e1000_nvm_override_microwire_large
162 } e1000_nvm_override;
165 e1000_phy_unknown = 0,
176 e1000_bus_type_unknown = 0,
179 e1000_bus_type_pci_express,
180 e1000_bus_type_reserved
184 e1000_bus_speed_unknown = 0,
190 e1000_bus_speed_2500,
191 e1000_bus_speed_5000,
192 e1000_bus_speed_reserved
196 e1000_bus_width_unknown = 0,
197 e1000_bus_width_pcie_x1,
198 e1000_bus_width_pcie_x2,
199 e1000_bus_width_pcie_x4 = 4,
200 e1000_bus_width_pcie_x8 = 8,
203 e1000_bus_width_reserved
207 e1000_1000t_rx_status_not_ok = 0,
208 e1000_1000t_rx_status_ok,
209 e1000_1000t_rx_status_undefined = 0xFF
210 } e1000_1000t_rx_status;
213 e1000_rev_polarity_normal = 0,
214 e1000_rev_polarity_reversed,
215 e1000_rev_polarity_undefined = 0xFF
216 } e1000_rev_polarity;
223 e1000_fc_default = 0xFF
227 e1000_ffe_config_enabled = 0,
228 e1000_ffe_config_active,
229 e1000_ffe_config_blocked
233 e1000_dsp_config_disabled = 0,
234 e1000_dsp_config_enabled,
235 e1000_dsp_config_activated,
236 e1000_dsp_config_undefined = 0xFF
240 struct e1000_rx_desc {
250 union e1000_rx_desc_extended {
274 #define MAX_PS_BUFFERS 4
276 union e1000_rx_desc_packet_split {
279 u64 buffer_addr[MAX_PS_BUFFERS];
306 struct e1000_tx_desc {
327 struct e1000_context_desc {
356 struct e1000_data_desc {
377 struct e1000_hw_stats {
455 struct e1000_phy_stats {
460 struct e1000_host_mng_dhcp_cookie {
472 struct e1000_host_command_header {
479 #define E1000_HI_MAX_DATA_LENGTH 252
480 struct e1000_host_command_info {
481 struct e1000_host_command_header command_header;
482 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
486 struct e1000_host_mng_command_header {
494 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
495 struct e1000_host_mng_command_info {
496 struct e1000_host_mng_command_header command_header;
497 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
500 #include "e1000_mac.h"
501 #include "e1000_phy.h"
502 #include "e1000_nvm.h"
503 #include "e1000_manage.h"
505 struct e1000_functions {
507 s32 (*init_mac_params)(
struct e1000_hw *);
508 s32 (*blink_led)(
struct e1000_hw *);
509 s32 (*check_for_link)(
struct e1000_hw *);
510 bool (*check_mng_mode)(
struct e1000_hw *hw);
511 s32 (*cleanup_led)(
struct e1000_hw *);
512 void (*clear_hw_cntrs)(
struct e1000_hw *);
513 void (*clear_vfta)(
struct e1000_hw *);
514 s32 (*get_bus_info)(
struct e1000_hw *);
515 s32 (*get_link_up_info)(
struct e1000_hw *, u16 *, u16 *);
516 s32 (*led_on)(
struct e1000_hw *);
517 s32 (*led_off)(
struct e1000_hw *);
518 void (*update_mc_addr_list)(
struct e1000_hw *, u8 *, u32, u32,
520 void (*remove_device)(
struct e1000_hw *);
521 s32 (*reset_hw)(
struct e1000_hw *);
522 s32 (*init_hw)(
struct e1000_hw *);
523 s32 (*setup_link)(
struct e1000_hw *);
524 s32 (*setup_physical_interface)(
struct e1000_hw *);
525 s32 (*setup_led)(
struct e1000_hw *);
526 void (*write_vfta)(
struct e1000_hw *, u32, u32);
527 void (*mta_set)(
struct e1000_hw *, u32);
528 void (*config_collision_dist)(
struct e1000_hw*);
529 void (*rar_set)(
struct e1000_hw*, u8*, u32);
530 s32 (*read_mac_addr)(
struct e1000_hw*);
531 s32 (*validate_mdi_setting)(
struct e1000_hw*);
532 s32 (*mng_host_if_write)(
struct e1000_hw*, u8*, u16, u16, u8*);
533 s32 (*mng_write_cmd_header)(
struct e1000_hw *hw,
534 struct e1000_host_mng_command_header*);
535 s32 (*mng_enable_host_if)(
struct e1000_hw*);
536 s32 (*wait_autoneg)(
struct e1000_hw*);
539 s32 (*init_phy_params)(
struct e1000_hw *);
540 s32 (*acquire_phy)(
struct e1000_hw *);
541 s32 (*check_polarity)(
struct e1000_hw *);
542 s32 (*check_reset_block)(
struct e1000_hw *);
543 s32 (*commit_phy)(
struct e1000_hw *);
544 s32 (*force_speed_duplex)(
struct e1000_hw *);
545 s32 (*get_cfg_done)(
struct e1000_hw *hw);
546 s32 (*get_cable_length)(
struct e1000_hw *);
547 s32 (*get_phy_info)(
struct e1000_hw *);
548 s32 (*read_phy_reg)(
struct e1000_hw *, u32, u16 *);
549 void (*release_phy)(
struct e1000_hw *);
550 s32 (*reset_phy)(
struct e1000_hw *);
551 s32 (*set_d0_lplu_state)(
struct e1000_hw *, bool);
552 s32 (*set_d3_lplu_state)(
struct e1000_hw *, bool);
553 s32 (*write_phy_reg)(
struct e1000_hw *, u32, u16);
554 void (*power_up_phy)(
struct e1000_hw *);
555 void (*power_down_phy)(
struct e1000_hw *);
558 s32 (*init_nvm_params)(
struct e1000_hw *);
559 s32 (*acquire_nvm)(
struct e1000_hw *);
560 s32 (*read_nvm)(
struct e1000_hw *, u16, u16, u16 *);
561 void (*release_nvm)(
struct e1000_hw *);
562 void (*reload_nvm)(
struct e1000_hw *);
563 s32 (*update_nvm)(
struct e1000_hw *);
564 s32 (*valid_led_default)(
struct e1000_hw *, u16 *);
565 s32 (*validate_nvm)(
struct e1000_hw *);
566 s32 (*write_nvm)(
struct e1000_hw *, u16, u16, u16 *);
569 struct e1000_mac_info {
591 u8 forced_speed_duplex;
594 bool arc_subsystem_valid;
595 bool asf_firmware_present;
599 bool disable_hw_init_bits;
600 bool get_link_status;
601 bool ifs_params_forced;
603 bool report_tx_early;
604 bool serdes_has_link;
605 bool tx_pkt_filtering;
608 struct e1000_phy_info {
611 e1000_1000t_rx_status local_rx;
612 e1000_1000t_rx_status remote_rx;
613 e1000_ms_type ms_type;
614 e1000_ms_type original_ms_type;
615 e1000_rev_polarity cable_polarity;
616 e1000_smart_speed smart_speed;
623 e1000_media_type media_type;
625 u16 autoneg_advertised;
628 u16 max_cable_length;
629 u16 min_cable_length;
633 bool disable_polarity_correction;
635 bool polarity_correction;
637 bool speed_downgraded;
638 bool autoneg_wait_to_complete;
641 struct e1000_nvm_info {
643 e1000_nvm_override
override;
655 struct e1000_bus_info {
657 e1000_bus_speed speed;
658 e1000_bus_width width;
666 struct e1000_fc_info {
673 e1000_fc_type original_type;
681 u8 __iomem *flash_address;
682 unsigned long io_base;
684 struct e1000_functions func;
685 struct e1000_mac_info mac;
686 struct e1000_fc_info fc;
687 struct e1000_phy_info phy;
688 struct e1000_nvm_info nvm;
689 struct e1000_bus_info bus;
690 struct e1000_host_mng_dhcp_cookie mng_cookie;
695 u16 subsystem_vendor_id;
696 u16 subsystem_device_id;
703 void e1000_pci_clear_mwi(
struct e1000_hw *hw);
704 void e1000_pci_set_mwi(
struct e1000_hw *hw);
705 s32 e1000_alloc_zeroed_dev_spec_struct(
struct e1000_hw *hw, u32 size);
706 s32 e1000_read_pcie_cap_reg(
struct e1000_hw *hw, u32 reg, u16 *value);
707 void e1000_free_dev_spec_struct(
struct e1000_hw *hw);
708 void e1000_read_pci_cfg(
struct e1000_hw *hw, u32 reg, u16 *value);
709 void e1000_write_pci_cfg(
struct e1000_hw *hw, u32 reg, u16 *value);