32 #include <linux/types.h>
39 #define er32(reg) __er32(hw, E1000_##reg)
40 #define ew32(reg,val) __ew32(hw, E1000_##reg, (val))
41 #define e1e_flush() er32(STATUS)
43 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
44 (writel((value), ((a)->hw_addr + reg + ((offset) << 2))))
46 #define E1000_READ_REG_ARRAY(a, reg, offset) \
47 (readl((a)->hw_addr + reg + ((offset) << 2)))
51 E1000_STATUS = 0x00008,
54 E1000_CTRL_EXT = 0x00018,
60 E1000_FEXTNVM4 = 0x00024,
61 E1000_FEXTNVM = 0x00028,
69 E1000_EIAC_82574 = 0x000DC,
72 E1000_EITR_82574_BASE = 0x000E8,
73 #define E1000_EITR_82574(_n) (E1000_EITR_82574_BASE + (_n << 2))
75 E1000_FCTTV = 0x00170,
79 E1000_TCTL_EXT = 0x00404,
82 E1000_LEDCTL = 0x00E00,
83 E1000_EXTCNF_CTRL = 0x00F00,
84 E1000_EXTCNF_SIZE = 0x00F08,
85 E1000_PHY_CTRL = 0x00F10,
86 #define E1000_POEMB E1000_PHY_CTRL
89 E1000_EEMNGCTL = 0x01010,
92 E1000_PBA_ECC = 0x01100,
94 E1000_FCRTL = 0x02160,
95 E1000_FCRTH = 0x02168,
96 E1000_PSRCTL = 0x02170,
97 E1000_RDBAL = 0x02800,
98 E1000_RDBAH = 0x02804,
99 E1000_RDLEN = 0x02808,
102 E1000_RDTR = 0x02820,
103 E1000_RXDCTL_BASE = 0x02828,
104 #define E1000_RXDCTL(_n) (E1000_RXDCTL_BASE + (_n << 8))
105 E1000_RADV = 0x0282C,
115 #define E1000_RDBAL_REG(_n) (E1000_RDBAL + (_n << 8))
116 E1000_KABGTXD = 0x03004,
117 E1000_TDBAL = 0x03800,
118 E1000_TDBAH = 0x03804,
119 E1000_TDLEN = 0x03808,
122 E1000_TIDV = 0x03820,
123 E1000_TXDCTL_BASE = 0x03828,
124 #define E1000_TXDCTL(_n) (E1000_TXDCTL_BASE + (_n << 8))
125 E1000_TADV = 0x0382C,
126 E1000_TARC_BASE = 0x03840,
127 #define E1000_TARC(_n) (E1000_TARC_BASE + (_n << 8))
128 E1000_CRCERRS = 0x04000,
129 E1000_ALGNERRC = 0x04004,
130 E1000_SYMERRS = 0x04008,
131 E1000_RXERRC = 0x0400C,
134 E1000_ECOL = 0x04018,
136 E1000_LATECOL = 0x04020,
137 E1000_COLC = 0x04028,
139 E1000_TNCRS = 0x04034,
141 E1000_CEXTERR = 0x0403C,
142 E1000_RLEC = 0x04040,
143 E1000_XONRXC = 0x04048,
144 E1000_XONTXC = 0x0404C,
145 E1000_XOFFRXC = 0x04050,
146 E1000_XOFFTXC = 0x04054,
147 E1000_FCRUC = 0x04058,
148 E1000_PRC64 = 0x0405C,
149 E1000_PRC127 = 0x04060,
150 E1000_PRC255 = 0x04064,
151 E1000_PRC511 = 0x04068,
152 E1000_PRC1023 = 0x0406C,
153 E1000_PRC1522 = 0x04070,
154 E1000_GPRC = 0x04074,
155 E1000_BPRC = 0x04078,
156 E1000_MPRC = 0x0407C,
157 E1000_GPTC = 0x04080,
158 E1000_GORCL = 0x04088,
159 E1000_GORCH = 0x0408C,
160 E1000_GOTCL = 0x04090,
161 E1000_GOTCH = 0x04094,
162 E1000_RNBC = 0x040A0,
167 E1000_MGTPRC = 0x040B4,
168 E1000_MGTPDC = 0x040B8,
169 E1000_MGTPTC = 0x040BC,
170 E1000_TORL = 0x040C0,
171 E1000_TORH = 0x040C4,
172 E1000_TOTL = 0x040C8,
173 E1000_TOTH = 0x040CC,
176 E1000_PTC64 = 0x040D8,
177 E1000_PTC127 = 0x040DC,
178 E1000_PTC255 = 0x040E0,
179 E1000_PTC511 = 0x040E4,
180 E1000_PTC1023 = 0x040E8,
181 E1000_PTC1522 = 0x040EC,
182 E1000_MPTC = 0x040F0,
183 E1000_BPTC = 0x040F4,
184 E1000_TSCTC = 0x040F8,
185 E1000_TSCTFC = 0x040FC,
187 E1000_ICRXPTC = 0x04104,
188 E1000_ICRXATC = 0x04108,
189 E1000_ICTXPTC = 0x0410C,
190 E1000_ICTXATC = 0x04110,
191 E1000_ICTXQEC = 0x04118,
192 E1000_ICTXQMTC = 0x0411C,
193 E1000_ICRXDMTC = 0x04120,
194 E1000_ICRXOC = 0x04124,
195 E1000_RXCSUM = 0x05000,
196 E1000_RFCTL = 0x05008,
198 E1000_RAL_BASE = 0x05400,
199 #define E1000_RAL(_n) (E1000_RAL_BASE + ((_n) * 8))
200 #define E1000_RA (E1000_RAL(0))
201 E1000_RAH_BASE = 0x05404,
202 #define E1000_RAH(_n) (E1000_RAH_BASE + ((_n) * 8))
203 E1000_SHRAL_PCH_LPT_BASE = 0x05408,
204 #define E1000_SHRAL_PCH_LPT(_n) (E1000_SHRAL_PCH_LPT_BASE + ((_n) * 8))
205 E1000_SHRAH_PCH_LTP_BASE = 0x0540C,
206 #define E1000_SHRAH_PCH_LPT(_n) (E1000_SHRAH_PCH_LTP_BASE + ((_n) * 8))
207 E1000_VFTA = 0x05600,
209 E1000_WUFC = 0x05808,
211 E1000_MANC = 0x05820,
212 E1000_FFLT = 0x05F00,
213 E1000_HOST_IF = 0x08800,
215 E1000_KMRNCTRLSTA = 0x00034,
216 E1000_MANC2H = 0x05860,
217 E1000_MDEF_BASE = 0x05890,
218 #define E1000_MDEF(_n) (E1000_MDEF_BASE + ((_n) * 4))
219 E1000_SW_FW_SYNC = 0x05B5C,
221 E1000_GCR2 = 0x05B64,
222 E1000_FACTPS = 0x05B30,
223 E1000_SWSM = 0x05B50,
224 E1000_FWSM = 0x05B54,
225 E1000_SWSM2 = 0x05B58,
226 E1000_FFLT_DBG = 0x05F04,
227 E1000_PCH_RAICC_BASE = 0x05F50,
228 #define E1000_PCH_RAICC(_n) (E1000_PCH_RAICC_BASE + ((_n) * 4))
229 #define E1000_CRC_OFFSET E1000_PCH_RAICC_BASE
230 E1000_HICR = 0x08F00,
233 #define E1000_MAX_PHY_ADDR 4
236 #define IGP01E1000_PHY_PORT_CONFIG 0x10
237 #define IGP01E1000_PHY_PORT_STATUS 0x11
238 #define IGP01E1000_PHY_PORT_CTRL 0x12
239 #define IGP01E1000_PHY_LINK_HEALTH 0x13
240 #define IGP02E1000_PHY_POWER_MGMT 0x19
241 #define IGP01E1000_PHY_PAGE_SELECT 0x1F
242 #define BM_PHY_PAGE_SELECT 22
243 #define IGP_PAGE_SHIFT 5
244 #define PHY_REG_MASK 0x1F
246 #define BM_WUC_PAGE 800
247 #define BM_WUC_ADDRESS_OPCODE 0x11
248 #define BM_WUC_DATA_OPCODE 0x12
249 #define BM_WUC_ENABLE_PAGE 769
250 #define BM_WUC_ENABLE_REG 17
251 #define BM_WUC_ENABLE_BIT (1 << 2)
252 #define BM_WUC_HOST_WU_BIT (1 << 4)
253 #define BM_WUC_ME_WU_BIT (1 << 5)
255 #define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
256 #define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
257 #define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
259 #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
260 #define IGP01E1000_PHY_POLARITY_MASK 0x0078
262 #define IGP01E1000_PSCR_AUTO_MDIX 0x1000
263 #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000
265 #define IGP01E1000_PSCFR_SMART_SPEED 0x0080
267 #define IGP02E1000_PM_SPD 0x0001
268 #define IGP02E1000_PM_D0_LPLU 0x0002
269 #define IGP02E1000_PM_D3_LPLU 0x0004
271 #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
273 #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
274 #define IGP01E1000_PSSR_MDIX 0x0800
275 #define IGP01E1000_PSSR_SPEED_MASK 0xC000
276 #define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
278 #define IGP02E1000_PHY_CHANNEL_NUM 4
279 #define IGP02E1000_PHY_AGC_A 0x11B1
280 #define IGP02E1000_PHY_AGC_B 0x12B1
281 #define IGP02E1000_PHY_AGC_C 0x14B1
282 #define IGP02E1000_PHY_AGC_D 0x18B1
284 #define IGP02E1000_AGC_LENGTH_SHIFT 9
285 #define IGP02E1000_AGC_LENGTH_MASK 0x7F
286 #define IGP02E1000_AGC_RANGE 15
289 #define E1000_VFTA_ENTRY_SHIFT 5
290 #define E1000_VFTA_ENTRY_MASK 0x7F
291 #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
293 #define E1000_HICR_EN 0x01
295 #define E1000_HICR_C 0x02
296 #define E1000_HICR_FW_RESET_ENABLE 0x40
297 #define E1000_HICR_FW_RESET 0x80
299 #define E1000_FWSM_MODE_MASK 0xE
300 #define E1000_FWSM_MODE_SHIFT 1
302 #define E1000_MNG_IAMT_MODE 0x3
303 #define E1000_MNG_DHCP_COOKIE_LENGTH 0x10
304 #define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0
305 #define E1000_MNG_DHCP_COMMAND_TIMEOUT 10
306 #define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64
307 #define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1
308 #define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2
311 #define E1000_STM_OPCODE 0xDB00
313 #define E1000_KMRNCTRLSTA_OFFSET 0x001F0000
314 #define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16
315 #define E1000_KMRNCTRLSTA_REN 0x00200000
316 #define E1000_KMRNCTRLSTA_CTRL_OFFSET 0x1
317 #define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3
318 #define E1000_KMRNCTRLSTA_TIMEOUTS 0x4
319 #define E1000_KMRNCTRLSTA_INBAND_PARAM 0x9
320 #define E1000_KMRNCTRLSTA_IBIST_DISABLE 0x0200
321 #define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000
322 #define E1000_KMRNCTRLSTA_K1_CONFIG 0x7
323 #define E1000_KMRNCTRLSTA_K1_ENABLE 0x0002
324 #define E1000_KMRNCTRLSTA_HD_CTRL 0x10
326 #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
327 #define IFE_PHY_SPECIAL_CONTROL 0x11
328 #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B
329 #define IFE_PHY_MDIX_CONTROL 0x1C
332 #define IFE_PESC_POLARITY_REVERSED 0x0100
335 #define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010
336 #define IFE_PSC_FORCE_POLARITY 0x0020
339 #define IFE_PSCL_PROBE_MODE 0x0020
340 #define IFE_PSCL_PROBE_LEDS_OFF 0x0006
341 #define IFE_PSCL_PROBE_LEDS_ON 0x0007
344 #define IFE_PMC_MDIX_STATUS 0x0020
345 #define IFE_PMC_FORCE_MDIX 0x0040
346 #define IFE_PMC_AUTO_MDIX 0x0080
348 #define E1000_CABLE_LENGTH_UNDEFINED 0xFF
350 #define E1000_DEV_ID_82571EB_COPPER 0x105E
351 #define E1000_DEV_ID_82571EB_FIBER 0x105F
352 #define E1000_DEV_ID_82571EB_SERDES 0x1060
353 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
354 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
355 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
356 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
357 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
358 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
359 #define E1000_DEV_ID_82572EI_COPPER 0x107D
360 #define E1000_DEV_ID_82572EI_FIBER 0x107E
361 #define E1000_DEV_ID_82572EI_SERDES 0x107F
362 #define E1000_DEV_ID_82572EI 0x10B9
363 #define E1000_DEV_ID_82573E 0x108B
364 #define E1000_DEV_ID_82573E_IAMT 0x108C
365 #define E1000_DEV_ID_82573L 0x109A
366 #define E1000_DEV_ID_82574L 0x10D3
367 #define E1000_DEV_ID_82574LA 0x10F6
368 #define E1000_DEV_ID_82583V 0x150C
370 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
371 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
372 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
373 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
375 #define E1000_DEV_ID_ICH8_82567V_3 0x1501
376 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
377 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
378 #define E1000_DEV_ID_ICH8_IGP_C 0x104B
379 #define E1000_DEV_ID_ICH8_IFE 0x104C
380 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
381 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5
382 #define E1000_DEV_ID_ICH8_IGP_M 0x104D
383 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
384 #define E1000_DEV_ID_ICH9_BM 0x10E5
385 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5
386 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF
387 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB
388 #define E1000_DEV_ID_ICH9_IGP_C 0x294C
389 #define E1000_DEV_ID_ICH9_IFE 0x10C0
390 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
391 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2
392 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
393 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
394 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
395 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
396 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
397 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525
398 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA
399 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB
400 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF
401 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0
402 #define E1000_DEV_ID_PCH2_LV_LM 0x1502
403 #define E1000_DEV_ID_PCH2_LV_V 0x1503
404 #define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A
405 #define E1000_DEV_ID_PCH_LPT_I217_V 0x153B
406 #define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A
407 #define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559
409 #define E1000_REVISION_4 4
411 #define E1000_FUNC_1 1
413 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
414 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
416 enum e1000_mac_type {
431 enum e1000_media_type {
432 e1000_media_type_unknown = 0,
433 e1000_media_type_copper = 1,
434 e1000_media_type_fiber = 2,
435 e1000_media_type_internal_serdes = 3,
436 e1000_num_media_types
439 enum e1000_nvm_type {
440 e1000_nvm_unknown = 0,
442 e1000_nvm_eeprom_spi,
447 enum e1000_nvm_override {
448 e1000_nvm_override_none = 0,
449 e1000_nvm_override_spi_small,
450 e1000_nvm_override_spi_large
453 enum e1000_phy_type {
454 e1000_phy_unknown = 0,
469 enum e1000_bus_width {
470 e1000_bus_width_unknown = 0,
471 e1000_bus_width_pcie_x1,
472 e1000_bus_width_pcie_x2,
473 e1000_bus_width_pcie_x4 = 4,
476 e1000_bus_width_reserved
479 enum e1000_1000t_rx_status {
480 e1000_1000t_rx_status_not_ok = 0,
481 e1000_1000t_rx_status_ok,
482 e1000_1000t_rx_status_undefined = 0xFF
485 enum e1000_rev_polarity{
486 e1000_rev_polarity_normal = 0,
487 e1000_rev_polarity_reversed,
488 e1000_rev_polarity_undefined = 0xFF
496 e1000_fc_default = 0xFF
500 e1000_ms_hw_default = 0,
501 e1000_ms_force_master,
502 e1000_ms_force_slave,
506 enum e1000_smart_speed {
507 e1000_smart_speed_default = 0,
508 e1000_smart_speed_on,
509 e1000_smart_speed_off
512 enum e1000_serdes_link_state {
513 e1000_serdes_link_down = 0,
514 e1000_serdes_link_autoneg_progress,
515 e1000_serdes_link_autoneg_complete,
516 e1000_serdes_link_forced_up
520 struct e1000_rx_desc {
530 union e1000_rx_desc_extended {
554 #define MAX_PS_BUFFERS 4
556 union e1000_rx_desc_packet_split {
559 __le64 buffer_addr[MAX_PS_BUFFERS];
578 __le16 header_status;
586 struct e1000_tx_desc {
607 struct e1000_context_desc {
624 __le32 cmd_and_length;
636 struct e1000_data_desc {
657 struct e1000_hw_stats {
723 struct e1000_phy_stats {
728 struct e1000_host_mng_dhcp_cookie {
740 struct e1000_host_command_header {
747 #define E1000_HI_MAX_DATA_LENGTH 252
748 struct e1000_host_command_info {
749 struct e1000_host_command_header command_header;
750 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
754 struct e1000_host_mng_command_header {
762 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
763 struct e1000_host_mng_command_info {
764 struct e1000_host_mng_command_header command_header;
765 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
769 struct e1000_mac_operations {
770 s32 (*id_led_init)(
struct e1000_hw *);
771 s32 (*blink_led)(
struct e1000_hw *);
772 bool (*check_mng_mode)(
struct e1000_hw *);
773 s32 (*check_for_link)(
struct e1000_hw *);
774 s32 (*cleanup_led)(
struct e1000_hw *);
775 void (*clear_hw_cntrs)(
struct e1000_hw *);
776 void (*clear_vfta)(
struct e1000_hw *);
777 s32 (*get_bus_info)(
struct e1000_hw *);
778 void (*set_lan_id)(
struct e1000_hw *);
779 s32 (*get_link_up_info)(
struct e1000_hw *, u16 *, u16 *);
780 s32 (*led_on)(
struct e1000_hw *);
781 s32 (*led_off)(
struct e1000_hw *);
782 void (*update_mc_addr_list)(
struct e1000_hw *, u8 *, u32);
783 s32 (*reset_hw)(
struct e1000_hw *);
784 s32 (*init_hw)(
struct e1000_hw *);
785 s32 (*setup_link)(
struct e1000_hw *);
786 s32 (*setup_physical_interface)(
struct e1000_hw *);
787 s32 (*setup_led)(
struct e1000_hw *);
788 void (*write_vfta)(
struct e1000_hw *, u32, u32);
789 void (*config_collision_dist)(
struct e1000_hw *);
790 void (*rar_set)(
struct e1000_hw *, u8 *, u32);
791 s32 (*read_mac_addr)(
struct e1000_hw *);
809 struct e1000_phy_operations {
810 s32 (*acquire)(
struct e1000_hw *);
811 s32 (*cfg_on_link_up)(
struct e1000_hw *);
812 s32 (*check_polarity)(
struct e1000_hw *);
813 s32 (*check_reset_block)(
struct e1000_hw *);
814 s32 (*commit)(
struct e1000_hw *);
815 s32 (*force_speed_duplex)(
struct e1000_hw *);
816 s32 (*get_cfg_done)(
struct e1000_hw *hw);
817 s32 (*get_cable_length)(
struct e1000_hw *);
818 s32 (*get_info)(
struct e1000_hw *);
819 s32 (*set_page)(
struct e1000_hw *, u16);
820 s32 (*read_reg)(
struct e1000_hw *, u32, u16 *);
821 s32 (*read_reg_locked)(
struct e1000_hw *, u32, u16 *);
822 s32 (*read_reg_page)(
struct e1000_hw *, u32, u16 *);
823 void (*release)(
struct e1000_hw *);
824 s32 (*reset)(
struct e1000_hw *);
825 s32 (*set_d0_lplu_state)(
struct e1000_hw *, bool);
826 s32 (*set_d3_lplu_state)(
struct e1000_hw *, bool);
827 s32 (*write_reg)(
struct e1000_hw *, u32, u16);
828 s32 (*write_reg_locked)(
struct e1000_hw *, u32, u16);
829 s32 (*write_reg_page)(
struct e1000_hw *, u32, u16);
830 void (*power_up)(
struct e1000_hw *);
831 void (*power_down)(
struct e1000_hw *);
835 struct e1000_nvm_operations {
836 s32 (*acquire)(
struct e1000_hw *);
837 s32 (*read)(
struct e1000_hw *, u16, u16, u16 *);
838 void (*release)(
struct e1000_hw *);
839 s32 (*update)(
struct e1000_hw *);
840 s32 (*valid_led_default)(
struct e1000_hw *, u16 *);
841 s32 (*validate)(
struct e1000_hw *);
842 s32 (*write)(
struct e1000_hw *, u16, u16, u16 *);
845 struct e1000_mac_info {
846 struct e1000_mac_operations ops;
848 u8 perm_addr[ETH_ALEN];
850 enum e1000_mac_type type;
868 #define MAX_MTA_REG 128
869 u32 mta_shadow[MAX_MTA_REG];
872 u8 forced_speed_duplex;
876 bool arc_subsystem_valid;
879 bool get_link_status;
881 bool serdes_has_link;
882 bool tx_pkt_filtering;
883 enum e1000_serdes_link_state serdes_link_state;
886 struct e1000_phy_info {
887 struct e1000_phy_operations ops;
889 enum e1000_phy_type type;
891 enum e1000_1000t_rx_status local_rx;
892 enum e1000_1000t_rx_status remote_rx;
893 enum e1000_ms_type ms_type;
894 enum e1000_ms_type original_ms_type;
895 enum e1000_rev_polarity cable_polarity;
896 enum e1000_smart_speed smart_speed;
903 enum e1000_media_type media_type;
905 u16 autoneg_advertised;
908 u16 max_cable_length;
909 u16 min_cable_length;
913 bool disable_polarity_correction;
915 bool polarity_correction;
916 bool speed_downgraded;
917 bool autoneg_wait_to_complete;
920 struct e1000_nvm_info {
921 struct e1000_nvm_operations ops;
923 enum e1000_nvm_type type;
924 enum e1000_nvm_override
override;
936 struct e1000_bus_info {
937 enum e1000_bus_width width;
942 struct e1000_fc_info {
949 enum e1000_fc_mode current_mode;
950 enum e1000_fc_mode requested_mode;
953 struct e1000_dev_spec_82571 {
958 struct e1000_dev_spec_80003es2lan {
962 struct e1000_shadow_ram {
967 #define E1000_ICH8_SHADOW_RAM_WORDS 2048
969 struct e1000_dev_spec_ich8lan {
970 bool kmrn_lock_loss_workaround_enabled;
971 struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS];
978 struct e1000_adapter *adapter;
981 u8 __iomem *flash_address;
983 struct e1000_mac_info mac;
984 struct e1000_fc_info fc;
985 struct e1000_phy_info phy;
986 struct e1000_nvm_info nvm;
987 struct e1000_bus_info bus;
988 struct e1000_host_mng_dhcp_cookie mng_cookie;
991 struct e1000_dev_spec_82571 e82571;
992 struct e1000_dev_spec_80003es2lan e80003es2lan;
993 struct e1000_dev_spec_ich8lan ich8lan;